Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Kevin Chiang

Chen-Jong Wang

Eric Chu

Ling-Hsin Tseng

Ken Yew

Kuo-Chyuan Tzeng

Tse-Liang Ying

Chen-Yong Lin

The present invention relates to a cooling system of a furnace, and more particularly, to a multi-cycle cooling system, located by the furnace door. The multi-cycle cooling system comprises the first gas cooling cycle, the second gas cooling cycle, the first liquid cooling cycle, the second liquid cooling cycle, the heat sinks and the heat insulation slot. When inside the process tube proceeds the high temperature process like depositing process, the first gas cooling cycle and the second gas cooling cycle are opened and the second liquid cooling cycle is closed at the same time. The second gas cooling cycle and the second liquid cooling cycle are assembled in the first flange, which is located on the process tube and contacts with the door. The first liquid cooling cycle in the second flange, which is located on the process tube and contacts with the first range, is always opened. When inside the process tube not proceeds the high temperature process, the first gas cooling cycle and the second gas cooling cycle are closed and the second liquid cycle is opened at the same time. The heat sinks and the heat insulation slot are on the door to increase the heat conduction efficiency of the door and to extend the lifetime of the elements on the door. The first liquid cooling cycle and the second cooling cycle are the independent cooling systems to each other. The first flange is located between the door and the second flange.

Cooling system for reducing particles pollution

The present invention relates to a cooling system of a furnace, more particularly, to a multi-cycle cooling system, located by the furnace door. The probability of pollution by particles can be decreased and the lifetime of the furnace devices can be extended by using different liquid and gas cycles, cooling the different steps the semiconductor processes in the furnace.

Within a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication there is formed contacting a second source/drain region within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device a storage capacitor prior to forming within a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device a pair of first source/drain regions. By employing such a process ordering, the field effect transistor (FET) logic semiconductor integrated circuit microelectronic device, and the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication, are fabricated with enhanced performance.

Embedded DRAM fabrication method providing enhanced embedded DRAM performance

A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.

Growing community of inventors

Hsin-Chu, Taiwan

Kevin Chiang