Siliconware Precision Industries Co., Ltd.

Kevin Chiang

Chien Ping Huang

Chien-Ping Huang

Vicky Liu

Candy Tien

Tom Tang

Tzong-Da Ho

Tzong-Dar Her

Jeng-Yuan Lai

Tzong Da Ho

Jenq-Yuan Lai

Nan-Jang Chen

A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Quad flat non-leaded semiconductor package and method of fabricating the same

A semiconductor package with an exposed heat spreader includes a substrate having a semiconductor chip adhered to a first surface of the substrate. The heat spreader includes an upper portion, a lower portion with an opening formed in the center for receiving the semiconductor chip, and a connecting portion for connecting the upper portion and the lower portion in a manner that the upper portion is raised to a height above the opening of the lower portion. The lower portion is formed with a plurality of positioning members outwardly extending from edges of the lower portion to prevent the heat spreader from being dislocated during a molding process, and further includes downward flutes formed on the periphery of the opening for enabling resin flow underneath the heat spreader. The upper portion of the heat spreader is exposed to an exterior of the semiconductor package to improve heat dissipation.

Semiconductor package having an exposed heat spreader

A BGA (Ball Grid Array) integrated circuit package is proposed, which is characterized in the use of a ground metallic layer adhered to a substrate. Moreover, the ground metallic layer can provide the semiconductor chip with a heat-dissipation path, allowing heat from the semiconductor chip during operation to be dissipated to the atmosphere via the ground metallic layer, so that the overall heat-dissipation efficiency can be increased. The ground metallic layer is formed with a chip-receiving cavity for accommodating a semiconductor chip mounted on the substrate. As the semiconductor chip is surrounded and in close proximity to the ground metallic layer, it can help reduce undesired simultaneous switching noise, crosstalk, and electromagnetic interference in the integrated circuit package.

Ball grid array integrated circuit package structure

An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant. With this integrated circuit package, no jig is required in the assembly of the integrated circuit package. Moreover, since there is no need to use adhesives to adhere the supportive legs onto the substrate, the integrated circuit package would not suffer from delamination as in the case of the prior art. The fully-exposed heat sink allows an increased heat-dissipating efficient as compared to the prior art.

Semiconductor package having a heat sink with an exposed surface

A tiny ball grid array package based on a substrate. The substrate has at least an insulation layer and two copper foils laminated together. A hole is formed near the center of the substrate. A second one of the copper foils is patterned into multiple conductive traces formed on a surface of the substrate, while a first one of the copper foils has a surface partly exposed. The first copper foil is coupled with the conductive traces by vias, meanwhile, the first copper foil is grounded to form a ground plane, so as to improve the electrically properties and the heat dissipation efficiency. Bonding pads are formed in one surface of a chip. This surface is thermal-conductively connected to the grounded level, and the bonding pads are located in the hole. The bonding pads are electrically connected to a near end of a conductive trace by a conductive wire, and solder balls are attached at a far end of the conductive trace. A molding material fills the hole and covers a surrounding area of the hole to protect the bonding pads, the conductive wire, and the conductive traces, so as to cover ajunction area of the chip and the ground plane.

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Taichung Hsien, Taiwan

Kevin Chiang