Oak Technology, Inc.

Other

Samsung Electronics Co., Ltd.

Marvell International Limited

Zoran Corporation

Qak Technology, Inc.

Kevin Chiang

Shengquan Wu

Amjad Z Qureshi

Hung Chou

Li-Huan Jen

Jhy-Ping Shaw

Kouchin Huang

Scott Li-Huan Jen

In one embodiment, the present invention includes a frequency divider circuit for dividing the frequency of an input signal by an odd value. In one embodiment, a frequency divider circuit includes a counter configured to receive a clock input signal and a divisor having an odd value. The counter counts clock cycles up to the divisor to generate a count. A control circuit is configured to receive the count, the divisor, and the clock input signal and generate one or more control signals to control a state of a clock output signal. A half cycle adjust circuit is configured to receive the clock input signal and the one or more control signals from the control circuit and provide an additional one-half cycle adjustment of the clock output signal. The frequency divider circuit may be a feed forward circuit with fast startup characteristics.

Circuits and methods for dividing frequency by an odd value

Present invention provides a method and apparatus for generating multiple phase shifted clocks with clocks delayed from EFM clock.

Write strategy with multi-stage delay cell for providing stable delays on EFM clock

A system and method for generating sample control signals for a sample and hold circuit used to control access to optical media is provided. The sample control signals are generated with sufficient duration (width) to adequately sample a reflected laser power signal. The sample control signals are defined relative to a laser power command signal generated in response to an internal data stream, rather than directly in response to the internal data stream, thereby allowing for more precise control of the sample control signals. As a result, substantial portions of each pulse of the reflected laser power signal can be sampled, without sampling transition noise that exists when the reflected laser power signal changes states. Generating the sample control signals from a laser power command signal, rather than the input data signal, more accurately time shifts the sampling command to the reflected laser power.

Read and write sample and hold signal generation

Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.

Pattern detection for computer segments

Method and system for determining varying widths of each of a sequence of signal components (marks and spaces) in an incoming digital signal stream and for indicating which mark widths and which space widths fall outside acceptable ranges. A pre-mark and pre-space are added to the front end of the recieved stream for alignment purposes. The width of each signal component (mark or space) is determined and compared with an acceptable range of mark widths or space widths. Each mark or space that lies outside an acceptable range has an indicium associated with this mark or space, indicating this non-compliance. The modified digital signal stream, including the indicia, is re-issued after a selected time delay for subsequent signal processing. A method for measurement or estimation of mark width and space width is presented.

Detection of EFM stream component widths

Method and system for receiving each data element of an array once and simultaneously forming an EDC error detection term, two ECC P-parity checkbytes and two ECC-Q-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor, by an ECC-P processor and by an ECC-Q processor and is processed in parallel and substantially simultaneously by the three processors to form an EDC error detection term and the ECC-P-parity and ECC-Q-parity checkbytes, using shift registers with feed-back and/or weighted summation of selected register contents.

Simultaneous processing for error detection and P-parity and Q-parity ECC encoding

A versatile serial to parallel interface capable of both receiving multiple types of input formats and operating in multiple operational modes includes a multiplexer, a signal generator, and a register. The multiplexer receives serial data from a plurality of possible data sources and, in response to a set of selection signals, outputs one of the sets of serial data to the signal generator. The signal generator thereafter forwards the serial data to the register for storage. In addition to forwarding the serial data to the register, the signal generator also generates clock and control signals. These signals are used to control the operation of the register to ensure proper serial to parallel conversion of the input serial data. In addition, these signals may also be provided to the source of the serial data to control the actions of the data source. The signal generator generates the clock and control signals in response to indication information provided to the signal generator. This indication information may include information relating to: (1) the desired mode of operation (e.g. slave or master) of the serial to parallel interface; and (2) the format (e.g. left justified or right justified) of the incoming serial data. This indication information gives the signal generator all of the information that it needs regarding the data source and the incoming data to generator all of the necessary signals for ensuring the proper operation of the serial to parallel interface.

Circuit for converting input serial data in a plurality of possible formats into output data in parallel format by interpreting input data format indication information

Method and system for receiving each data element of an N&times;M array once and simultaneously forming an EDC error detection term and two ECC P-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor and by an ECC processor and processed in parallel by the two processors to form the EDC error detection term and two ECC P-parity checkbytes.

Simultaneous processing for error detection and P-parity ECC encoding

A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K&plus;N parameter values.

Write strategy and timing

A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s and s are computed for a sequence of data elements, using a selected primitive &agr; that satisfies a selected primitive polynomial relation p(&agr;)&equals;0. Each of two checkbytes, c and c is expressed as a linear combination of the syndromes s and s where each coefficient of each linear combination is expressed as a single power of the primitive &agr; and is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.

Modified Reed-Solomon multiplication

Method and system for estimating processing time delay &Dgr;t of a selected signal processing device and temperature T of the device. A selected input signal is received by a first sub-system that includes the selected device and by a second sub-system having a controllable time delay, producing first and second sub-system output signals. The first and second sub-system output signals are compared to estimate the time delay of the selected device. A known relationship T&equals;f(&Dgr;t ) is used to estimate temperature of the selected device and to determine whether this temperature is higher than a permitted or threshold device operating temperature. First and second signals, having the same or different shape parameters, may be processed by the system, and a statistical average of estimated device time delay can be computed to estimate device temperature.

Estimation of device temperature

Method and system for limiting the effects of data bit cell errors or error control bit errors that are uncorrectable in a computer. When a corrupted data bit cell is found, the content of the corrupted data bit cell is replaced by an error control bit from an error control bit segment associated with the data bit segment, the error control procedure for this (modified) data bit segment is disabled, and this modified data bit segment is flagged to indicate that the error control procedure for this modified data bit segment is disabled. A corrupted error control bit cell is processed in a similar manner. When a correctable bit error, not stored in a corrupted bit cell, is found, the bit error is corrected by the error control mechanism.

Replacement of bad data bit or bad error control bit

System and method for improved formation of a Q-parity checkbyte matrix used for error control for a sequence of message bytes and error control bytes, using an algorithm, rather than a lookup table, to determine the order of the words used for the sequence. Entries of a Reed-Solomon parity check rectangular array are set up sequentially and diagonally, including the syndrome bytes and checkbytes to be used for error detection, so that all matrix entries can be written to, or read from, a computer memory in a stream of bytes whose order is determined by the algorithm without reference to a lookup table.

ECC Q-parity checkbyte indexing

Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.

Selectively accessible memory banks for operating in alternately reading or writing modes of operation

A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s and s , are computed for a sequence of data elements, using a selected primitive a that satisfies a selected primitive polynomial relation p(&agr;)&equals;0. Each of two checkbytes, c and c , is expressed as a linear combination of the syndromes s and s , where each coefficient of each linear combination is expressed as a single power of the primitive &agr;, which is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.

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Fremont, CA, United States of America

Kevin Chiang