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Kevin Charles Gower

Warren Edward Maule

Frank David Ferraiolo

Daniel Mark Dreps

Paul William Coteus

Mark William Kellogg

Robert Brett Tremaine

Luis Alfonso Lastras-Montano

Dustin James VanStee

Timothy Jay Dell

Patrick James Meaney

Kyu-hyoun Kim

Robert J Reese

Bruce G Hazelzet

Kirk David Lamb

Gareth Geoffrey Hougham

Eric Eugene Retter

Charles Arthur Kilmer

Shawn Anthony Hall

Mark Andrew Brittain

Kevin W Kark

Dale J Pearson

Eldee Stephens

Roger A Rippens

James Stephen Fields, Jr

Martin L Schmatz

Hillery C Hunter

Edgar Rolando Cordero

Vesselina K Papazova

Michael Raymond Trombley

David J Perlman

Thomas M Cowell

Frank LaPietra

James A O'Connor

Kenneth Lee Wright

George L Chiu

Thomas J Griffin

Peter L Buchmann

Thomas Basil Smith, Iii

Kyu-Hyoun Kim

Elianne A Bravo

Ravi Kumar Arimilli

Michael Anthony Sorna

Scott Barnett Swaney

Bradley David McCredie

Thomas J Dewkett

Jonathan Yang Chen

Luiz Carlos Alves

Michael Kevin Kerr

James A Mossman

Juergen Saalmueller

William J Clarke

Carl E Love

William M Zevin

David William Mann

Faisal A Ahmad

Anish T Patel

Frank D Ferriaolo

John Steven Dodson

Ashish Jagmohan

Michele M Franceschini

Albert Manhee Chu

Gary A Van Huben

Michael Joseph Carnevale

Edward N Cohen

Michael B Spear

John E Campbell

Roger Paul Gregor

Peter Matthew Thomsen

Donald J Ziebarth

Steven J Hnatko

Thomas Charles Brennan

Gary Alan Peterson

William J Scarpero, Jr

Toru Kobayashi

Thomas G Mitchell

Daniel John Kolor

Louis J Bosch

Kenneth Y Chan

Glenn E Holmes

Richard Bogholtz, Jr

Karl D Loughner

Luis C Alves

David T Perlman

ChiWei Yung

David J Perhnan

John M Deegan

Swati Sathaye

Hideo Sawamoto

Erik Victor Kusko

Lisa C Gower

Luiz Alves

James O`CONNOR

An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.

Configurable differential to single ended IO

Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.

Homogeneous recovery in a redundant memory system

Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.

Isolation of faulty links in a transmission medium

Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or the latency window of a memory controller such that a data signal and a data strobe signal are received by the memory controller within the latency window of the memory controller.

Memory interface having extended strobe burst for read timing calibration

Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing based on the removing any stale data being complete.

Heterogeneous recovery in a redundant memory system

A computer implemented method for providing homogeneous recovery in a redundant memory system. The method includes receiving a notification that a memory channel has failed, where the memory channel is one of a plurality of memory channels in a memory system. New operations are blocked from starting on the memory channels in response to the notification, and any pending operations on the memory channels are completed in response to the notification. A recovery operation is performed on the memory channels in response to the completing. The new operations are started on at least a first subset of the memory channels in response to the recovery operation completing. The memory system is configured to operate with the first subset of the memory channels.

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Advanced memory device having improved performance, reduced power and increased reliability

A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

Memory interface having extended strobe burst for write timing calibration

Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.

A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

System, method and storage medium for providing fault detection and correction in a memory subsystem

Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Failing bus lane detection using syndrome analysis

A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Error correcting code protected quasi-static bit communication on a high-speed bus

A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and 'n' subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the 'n' subsequent data transfers make up a data frame, where &#x201c;n&#x201d; is greater than zero.

Providing frame start indication in a memory system having indeterminate read data latency

A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Strobe offset in bidirectional memory strobe configurations

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Kevin Charles Gower