Altera Corporation

International Business Machines Corporation

Kevin Chan

Terry Borer

Stephen D Brown

Vaughn Betz

Mark Bourgeault

Ian Chesal

David Wolk Mendel

Gregg William Baeckler

Deshanand Pratap Singh

James G Schleicher

Babette Van Antwerpen

Richard Yuan

Gabriel Quan

Mike Hutton

Boris Ratchev

Yaska Sankar

Valavan Manohararajah

David Karchmer

Michael Starkey

Andrew Leaver

Dirk Alexander Seelemann, Ii

Ivan Hamer

Paul McHardy

Jason Govig

Karl Schabas

Minh V Mac

Wassim Melhem

Subianto Windoro

Irene Sujanto

Sheac Yee Lim

Vito Spatafora

A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Method and apparatus for performing incremental compilation using structural netlist comparison

A method for designing a system on a target device includes compiling an intellectual property (IP) core to be implemented on the target device such that it satisfies user specified requirements for the system. User logic is compiled after the IP core has been compiled to satisfy user specified requirements for the system.

Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow

Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.

Method and apparatus for performing incremental compilation

Techniques are provided for converting a circuit design file so that it is compatible with a new programmable IC. Black box declarations and instances of black boxes in the circuit design file are located automatically. Then, information about the function and structure of the black boxes is gathered from various user files. This information is used to convert the black box declarations and instances into equivalent declarations and instances that are compatible with the new programmable IC. The design conversion process is performed quickly and automatically with minimal user input. User input is only needed to identify recognized black boxes.

Techniques for editing circuit design files to be compatible with a new programmable IC

A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.

Method and apparatus for performing logic replication in field programmable gate arrays

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.

Method and apparatus for performing incremental compilation on field programmable gate arrays

The invention pertains to a computer tutorial system wherein software product training is provided interactively by guiding the user, for example, through one or more examples or applications that can be created in and/or using the product. More particularly, the invention involves a computer implemented, interactive tutorial system providing online instruction in conjunction with a contemporaneously operating software product to, for example, create such examples or applications and the tutorial system further providing for the creation of such examples or applications in and/or using the product.

Interactive tutorial

Growing community of inventors

Scarborough, Canada

Kevin Chan