National Semiconductor Corporation

Kevin Carl Brown

Paul McKay Moore

Henry Wei-Ming Chung

Richard Luttrell

Lisa Maire Brown

Rashid Bashir

Vassili M Kitch

Wipawan Yindeepol

Joel M McGregor

Joost J Vlassak

Joseph Anthony DeSantis

Satyendra S Sethi

Anand J Bariya

A via is formed in a semiconductor device using a self-aligned copper-based pillar to connect upper and lower copper interconnect layers separated by a dielectric. The lower interconnect layer is formed on an underlying layer. The copper-based via pillar is formed on the lower interconnect layer. The upper interconnect layer is formed to make electrical contact to the exposed upper surface of the via pillar. Conductive diffusion barrier material is formed on vertical sidewalls of the lower interconnect layer.

Self-aligned copper interconnect architecture with enhanced copper diffusion barrier

A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) CMP of dielectric layer underlying the metal following SOG planarization; 2) CMP of dielectric layer underlying the metal following formation of vias; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes. First, the REC coats the freshly deposited metal layer immediately following deposition, preserving the metal in its highly reflective state. Second, the REC generates constructive interference of light reflected by the metal layer. This constructive interference can generate reflectivity greater than that of the bare metal surface.

Silicon interconnect passivation and metallization process optimized to maximize reflectance

A method for determining the temperature of a wafer during processing is disclosed. A test wafer is specially prepared in conjunction with a calibration chart. The difference in stack sheet resistance of the test wafer before and after processing is plotted onto the calibration chart to determine the temperature of the test wafer during processing.

Method of wafer temperature measurement

A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes. First, the REC coats the freshly deposited metal layer immediately following deposition, preserving the metal in its highly reflective state. Second, the REC generates constructive interference of light reflected by the metal layer. This constructive interference can generate reflectivity greater than that of the bare metal surface.

Interconnect passivation and metallization process optimized to maximize reflectance

Self-aligned copper interconnect architecture with enhanced copper

Combined vibrating beeper and infant monitor system

A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line. Selected portions of the etch stop layer are removed to expose the protection surface of the composite protection/metal line and portions of the boundary layer, while leaving the etch stop spacers. Portions of the boundary layer between the etch stop spacers are removed. A layer of via dielectric is formed that covers, and extends above, the line. A portion of the via dielectric layer above the composite protection/metal line is removed, exposing a portion of the protection surface of the composite protection/metal line. Finally, a portion of the protection surface from the composite protection/metal line is removed, leaving the metal portion of the line only.

Integrated circuits with borderless vias

A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate. The second nitride layer is then anisotropically etched to remove the nitride from the exposed horizontal surface of the hardmask oxide and the buried oxide in the bottom of the trench, but leaving silicon nitride on the vertical sidewall portions of the hardmask oxide, on the sidewalls of the first nitride layer on the sidewalls of the field oxide and on the trench lining oxide. A layer of polysilicon is then deposited to fill the trench and etched back such that the top surface of the polysilicon substantially corresponds to the top surface of the layer of field oxide. The hardmask oxide layer is then removed and the top surface of the polysilicon layer is oxidized.

Method of forming and planarizing deep isolation trenches in a

An antireflective coating used in the photolithography process is applied and removed in a plasma reactor. The halocarbon plasma polymer such as fluorocarbon plasma polymer of the present invention provides an improved antireflective coating.

Growing community of inventors

Sunnyvale, CA, United States of America

Kevin Carl Brown