Intel Corporation

Kevin C Kahn

Prashant R Chandra

Donald B Alpert

Gary N Hammond

Tsung-Yuan Charles Tai

David B Andersen

Charles L Brabenac

Harsh Sharangpani

Konrad K Lai

Ajay V Bhatt

Kenneth D Shoemaker

Efraim Kugman

Vladimir Yudovich

Eran Galil

Naama Zolotov

Yoni Dishon

Elli Bagelman

Steven Bernard McGowan

George W Cox

David G Carson

Jay Sethuram

Herman D D'Hooge

John A Bayliss

Farhad Mighani

Steve McGowan

David Eckhardt

Haim Sadger

Bert E Forbes

Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.

Multi-protocol I/O interconnect including a switching fabric

Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.

Multi-protocol tunneling over an I/O interconnect

Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for configuring a multi-protocol I/O interconnect may include identifying a plurality of switches of a switching fabric of a multi-protocol I/O interconnect, and configuring a path from a port of a first switch of the plurality of switches to a port of a second switch of the plurality of switches. Packets of a first protocol and packets of a second protocol, different from the first protocol, may be simultaneously routed over the path. Other embodiments may be described and claimed.

Multi-protocol I/O interconnect architecture

A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.

Unified multi-transport medium connector architecture

Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for managing flow across the multi-protocol I/O interconnect may include providing, by a first port of a switching fabric of a multi-protocol interconnect to a second port of the switching fabric, a first credit grant packet and a second credit grant packet as indications of unoccupied space of a buffer associated with a path between the first port and a second port, and simultaneously routing a first data packet of a first protocol and a second data packet of a second protocol, different from the first protocol, on the path from the second port to the first port based at least in part on receipt by the second port of the first and second credit grant packets. Other embodiments may be described and claimed.

Multi-protocol I/O interconnect flow control

A method for managing an asynchronous transfer mode (ATM) cell includes transmitting an ATM cell from a server system to a broadband modem. The ATM cell is forwarded from the broadband modem to a client system.

Method and apparatus for extending point-to-point/asynchronous transfer mode services to client computer systems

A method, apparatus, and system are provided for transmitting an Asynchronous Transfer Mode (ATM) cell from a server system to a broadband modem and forwarding the ATM cell from the broadband modem to a client system. According to one embodiment, a Broadband Modem Access Protocol (BMAP) unit is used to discover the identity of the broadband modem.

Extending point-to-point/asynchronous transfer mode services to client computer systems

An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

Article for providing event handling functionality in a processor supporting different instruction sets

Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

Method and apparatus for providing event handling functionality in a computer system

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Portland, OR, United States of America

Kevin C Kahn