International Business Machines Corporation

Kevin C Huang

Gregory Scott Still

Robert Huntington Grant

Agnes Yee Ngai

Thomas Jefferson Sandridge

Barbara A Hall

Jacob Thomas Covell

John David Jabusch

Richard J Gusefski

David A Wise

James William Ryder

Chon I Lei

Mark Alan Bilansky

Timothy J McNamara

Edward James Stavana

John G Santoni

Thang T Do

James E Bohner

Karl H Kutz

Victoria E Seals

A computer-implemented method includes: creating a virtualized copy of a mesh network including devices; measuring an unpatched performance metric value for the virtualized copy of each of the devices; applying a first software patch to the virtualized copy of each of the devices; measuring a patched first performance metric value for the virtualized copy of each of the devices; comparing, for each of the devices, the patched performance metric value to the unpatched performance metric value; and preventing the application of the first software patch to a first device of the devices as a result of the comparing.

Software patch optimization

A system and method is provided for communicating data and control information between two systems, each system including a communication protocol stack, such as an advanced program to program communication (APPC) protocol stack which includes an I/O interface layer with modules for OPEN, GET, PUT, UPDATE, RELEASE, DELETE, CLOSE, and an OPC interface to a serial optical bus. Dual control and data paths are established from, for example, a client system to a single agent on a target system, the control path including a protocol stack and a data path avoiding at least one layer of the protocol stack. Packets of control information for a given process are transferred on the control path, and packets of data information are transferred on the data path. Communications are sychronized so that the client and target systems send and receive communications packets on the same one of the two paths.

Dual communication services interface for distributed transaction

A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.

Central processing unit checkpoint retry for store-in and store-through

A computing system constructed of multiple processing elements containing private storage, attached to a shared global storage, is called a closely-coupled system. Each processing element may be a single processing unit (PU) with private storage, or a tightly coupled multi-processor unit with private storage. Either type of processing element will be referred to as a Central Processor Complex (CPC), the computing system complex as a whole is referred to as a sysplex. IBM ESA/390 processors provide examples of both single and multi-processor CPC's. For a highly-available shared storage for data-sharing in a multi-processing element environment, highly-available shared storage is provided by a duplexed controllers with non-volatile storage, which is accessed by tightly connected Processing Elements as a single logical copy. Our duplexed controllers provide not only the shared data but also the control information necessary for multi-Processing Element data management with speed-matching processor. The duplexed controllers, including a primary and backup controller, are always synchronized to execute each message command to ensure that they do not diverge. Each controller of the duplexed controller receives its own command from a Processing Element and reaches consensus with other controller to synchronize command execution and return a response code to the Processing Element. To sequence and synchronize the command execution by each of the duplexed controller, a tightly-synchronized Sysplex timer is used to time-stamp each command and response so that the duplexed controllers will run in synchronism. When an 'out of sync' condition is detected by a SSC, the monitoring information of SSC and integrated SP, and the result of diagnostics are used to determine the faulty SSC of a the duplexed SSC.

Shared storage controller for dual copy shared data

Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.

Apparatus and method for simultaneously presenting error interrupt and

An inpage buffer is used between a cache and slower storage device. When a processor requests data, the cache is checked to see if the data is already in the cache. If not, a request for the data is sent to the slower storage device. The buffer receives the data from the slower storage device and provides the data to the processor that requested the data. The buffer then provides the data to the cache for storage provided that the cache is not working on a separate storage request from the processor. The data will be written into the cache from the buffer when the cache is free from such requests. The buffer is also able to provide data corresponding to subsequent requests provided it contains such data. This may happen if a request for the same data occurs, and the buffer has not yet written the data into the cache. It can also occur if the areas of the cache which can hold data from an area of the slower storage is inoperable for some reason. The buffer acts as a minicache when such a catastrophic error in the cache occurs.

Cache bypass apparatus

Programmable masks at ascending levels of processing machine functionality support the programmed injection of errors in response to machine events and machine states and in synchronism with machine operation. Provision is made for varying characteristics of injected errors through a programmable error mask and through generation of an injected error wave form having variable temporal and duration characteristics.

Event-controlled error injection system

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Kevin C Huang