Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Kevin C Heuer

Tarun Nakra

Robert A McGowan

Eric C Quinnell

Robert N Ehrlich

Akhil Arunkumar

Khang Nguyen

Embodiments of the present system and method provide cache replacement in a victim exclusive cache using a snoop filter where replacement information is not lost during a re-reference back to the CPU. Replacement information is stored in a snoop filter, meaning that historical access data may be fully preserved and allows for more flexibility in the LLC re-insertion points, without additional bits stored in a L2 cache. The present system and method further include snoop filter replacement technique. The present system and method passes replacement information between a snoop filter and a victim exclusive cache (e.g., LLC) when transactions move cachelines to and from a master CPU. This maintains and advances existing replacement information for a cacheline that is removed from the victim exclusive cache on a read, as well as intelligently replaces and ages cachelines in the snoop filter.

Snoop filter with stored replacement information, method for same, and system including victim exclusive cache and snoop filter shared replacement policies

According to one general aspect, an apparatus may include a cache and a cache replacement unit. The cache may be arranged in a plurality of cache sets each configured to store data. A number of cache sets are designated as leader cache sets and each leader cache set is associated with a first replacement policy or a second replacement policy. The cache replacement unit may be configured to monitor an effectiveness of the first replacement policy and, at least, the second replacement policy to accurately predict cache line replacement. The cache replacement unit may be configured to select the first replacement policy or the second replacement policy to be a dominant replacement policy. The cache replacement unit may be configured to dynamically scale the number of cache sets that are designated as leader cache sets based at least in part upon the effectiveness of the dominant replacement policy.

System and method for adaptive cache replacement with dynamic scaling of leader sets

Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache's CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus.

Cache result register for quick cache information lookup

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Kevin C Heuer