International Business Machines Corporation

Kevin Barnett

Debapriya Chatterjee

John Andrew Schumann

Karen E Yokum

Bryant Cockcroft

Paul Umbarger

Paul Frank Lecocq

Tharunachalam Pindicura

Jeffrey W Kellington

Lance G Hehenberger

Jamory Hawkins

Lawrence Leitner

Omesh Bajaj

Larry Scott Leitner

Piriya K Hall

Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.

Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Method and system for detection of thread stall

An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

Identifying translation errors

A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

Precise verification of a logic problem on a simulation accelerator

Growing community of inventors

Austin, TX, United States of America

Kevin Barnett