Intel Corporation

Kevin B Theobald

Tsung-Yuan Charles Tai

Ren Wang

Zeshan A Chishti

Robert P Adler

Rupin H Vakharwala

Aamer Jaleel

Erik Hallnor

Zhaojuan Bian

Robert J Toepfer

Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.

Shared flow control credits

Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.

Managing shared cache by multi-core processor

Growing community of inventors

Hillsboro, OR, United States of America

Kevin B Theobald