Intel Corporation

Kevin B Smith

Seth Abraham

Zia Ansari

Robert Valentine

Jason W Brandt

Jonathan D Combs

Maxim Loktyukhin

Clark F Nelson

In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.

Conditional execution support for ISA instructions using prefixes

A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types.

Method and apparatus for generating multiple processor-specific code segments in a single executable

A computer-implemented method identifies a code segment which is to be customized to a plurality of different processor types. The method generates object code for the code segment, including generating a plurality of sections for the code segment, each of the plurality of sections being object code for the code segment customized for one of the plurality of different processor types, and generating a control section that causes a selected one of the plurality of sections to be called during execution of the object code in accordance with an executing processor's processor type.

Method and apparatus for supporting multiple processor-specific code

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Hillsboro, OR, United States of America

Kevin B Smith