Sun Microsystems, Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Azul Systems, Inc.

Kevin B Normoyle

Satyanarayana Nishtala

Zahir Ebrahim

William C Van Loo

Louis F Coffin, Iii

Mark Douglas Hummel

Anthony Asaro

Rajasekhar Cherabuddi

Leslie Dean Kohn

Jack H Choquette

Charles E Narad

Michael A Csoppenszky

Paul N Loewenstein

Robert G Hathaway

Tzungren A Tzeng

Jui-Cheng Su

Gil Tene

Mark Fowler

David A Kruckemyer

Sun-den Chen

Brian McGee

Meera Kasinathan

William Van Loo

David A Penry

Jaybharat Boddu

Alex S Han

Anup K Sharma

Murali Sundaresan

Cliff N Click, Jr

Scott D Sellers

Massimo Sutera

Bruce E Petrick

Norman Rubin

Prakash Narain

Lan Lee

Manuel Olivier Gautho

John Phillips

Anuradha N Moudgal

Sung-Hun Oh

Elias Atmeh

Sreenivas Aerra Reddy

Sharath Raghava

Christopher Furman

Sutikshan Bhutani

David Kruckernyer

David A Bunsey, Jr

Daniel Y Cheung

Shi-Chin Ou-Yang

Ivana Capellano

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Memory pools in a memory model for a unified computing system

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Memory heaps in a memory model for a unified computing system

Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Managing coherent memory between an accelerated processing device and a central processing unit

Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.

Shared memory space in a unified memory model

Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.

Visibility ordering in a memory model for a unified computing system

Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.

Cache management for memory operations

A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory module

Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.

Ordering operation

A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines

Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module

A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

Speculative multiaddress atomicity

Growing community of inventors

Santa Clara, CA, United States of America

Kevin B Normoyle