International Business Machines Corporation

Kevin Arthur Chiarot

David Scott Ray

Shih-Hsiung Stephen Tung

David Andrew Schroter

Michael John Mayfield

Barry Duane Williamson

A James Van Norstrand, Jr

Milford John Peterson

Theodore J Schmitt

Era Kasturia Nangia

Brian R Konigsburg

Avijit Saha

Douglas Craig Bossen

Robert Michael Dinkjian

Richard J Schmalz

Arnold S Tran

Dave Stephen Levitan

Namratha Rajasekharaiah Jaisimha

A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to the set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register. The IPU may include an address incrementer suitable for generating a next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses. In this embodiment, the next instruction address comprises an input to the multiplexer. The IPU may further include selector logic adapted to select the next instruction address as the output of the multiplexer if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The selector logic is adapted to select as the output of the multiplexer the branch target address of the first instruction predicted to be taken if the number of branch instructions in the set of instructions for which branch instruction information must be recorded does not exceed the capacity of IPU to record the branch instruction information in a single cycle.

Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions

A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

Recovery mechanism for L1 data cache parity errors

The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists. The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are canceled.

Apparatus and method for tracking out of order load instructions to

An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.

Data processing system having an apparatus for out-of-order register

One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

System for providing high performance speculative processing of complex

An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.

Instruction pre-fetching of a cache line within a processor

A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ('inevitable-speculative') and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.

Prefetching instructions between caches

An Access List Entry Token (ALET) access look-aside facility is used to look at all entries in the access Look-Aside Buffer (ALB) and select a Segment Table Destination (STD) for use in Dynamic Address Translation (DAT). At the same time that address generation is done to form the virtual address used for DAT, the content of the access register (i.e., the ALET) to be used for the access is sent to the ALB. When the AR-specified STD is to be used for DAT, the ALET sent to the ALB is simultaneously compared with all the ALETs in the ALB. If the ALET compares with an ALET in an ALB entry, the STD associated with that entry is selected for use in the storage access.

Access look-aside facility

An improved DLAT structure distinguishes between address spaces and data spaces. The DLAT structure classifies data spaces by one or more space identifications which control assignment of virtual page addresses to DLAT rows. In one embodiment, a 'private space bit' is used to select different DLAT addressing algorithms. In another embodiment, data spaces are sub-classified using space identification bits, and for each sub-class, a unique algorithm is selected based on the page address bits. An Exclusive OR function is used to generate the DLAT selection bits. This approach minimizes private space synonyms while maximizing common space synonyms. The result is improved performance since the former minimizes thrashing and the latter maximizes the value of the DLAT common bit.

Growing community of inventors

Pflugerville, TX, United States of America

Kevin Arthur Chiarot