International Business Machines Corporation

Kevin Anthony Pasnik

Viktor Sandor Gyuris

Harrell Hoffman

Gernot Eberhard Guenther

John Henry Westermann, Jr

Thomas John Tryt

John Henry Westerman, Jr

Daniel R Crouse, Ii

Gernot E Günther

A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size

A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.

Instruction encoding in a hardware simulation accelerator

A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Hardware accelerator with a single partition for latches and combinational logic

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Westford, VT, United States of America

Kevin Anthony Pasnik