United States of America As Represented by the Secretary of the Air Force

Kevin Anthony Kwiat

Charles Kamhoua

Laurent Njilla

Travis Schulze

Yiyu Shi

Praveen Rao

Ali S Sabbir

Benjamin C Hardekopf

Luke Kwiat

Kaliappanadar Ravindran

The invention is a secure logic chip with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a secure logic chip design such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several features including randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.

Secure logic chip for resisting hardware trojan induced leakage in combinational logic

Secure logic chip for resisting hardware trojan induced leakage in combinational logics

A cyberthreat detection method and system includes a distributed file system and a commodity cluster. The commodity cluster has a plurality of servers. A data array of key-value pairs related to social media is received; it stores a plurality of predetermined ground predicates. A ground predicate graph is constructed for each user then partitioned into balanced portions Peach corresponding to a server and the ground predicates stored on that server. In parallel on each server, a plurality of leaned rules are determined for the files stored on that server. From a union of the plurality of learned rules, the system determines a respective weight for each of the learned rules. The plurality of rules are ranked in order of accuracy by the plurality of weights.

Method of cyberthreat detection by learning first-order rules on large-scale social media

The invention comprises a system and article of manufacture to discover potential cyber threats on Twitter. The invention provides a unified framework for modeling and reasoning about the veracity of tweets to discover suspicious users and malicious content. The invention builds on the concept of Markov logic networks (MLNs) for knowledge representation and reasoning under uncertainty.

System and article of manufacture to analyze twitter data to discover suspicious users and malicious content

Apparatus, method and article of manufacture providing a randomized encoding scheme for sequential logics, for resistance to data leakage. Invention employs dual-rail encoding to randomize the information in the chip, and employs three-dimensional integration technology to protect the critical information that is needed to decode the data anywhere on-chip. With the present invention, even when the entire design is completely known to the attacker who also has full access to the outsourced portion, it is still not always possible to identify the information in the chip using data leakage Trojans.

Apparatus, method and article of manufacture for partially resisting hardware trojan induced data leakage in sequential logics

A method for enhancing security in a cloud computing system by allocating virtual machines over hypervisors, in a cloud computing environment, in a security-aware fashion. The invention solves the cloud user risk problem by inducing a state such that, unless there is a change in the conditions under which the present invention operates, the cloud users do not gain by deviating from the allocation induced by the present invention. The invention's methods include grouping virtual machines of similar loss potential on the same hypervisor, creating hypervisor environments of similar total loss, and implementing a risk tiered system of hypervisors based on expense factors.

Security method for allocation of virtual machines in a cloud computing network

A computer and software method and apparatus for distributed data processing which provides agreement between data sources (sensors) and data sinks (actuators) as to what data has been written into a shared buffer. The invention further provides methods and means for meeting data timeliness requirements. Invention employs a programming primitive which recognizes semantics so as to provide a consistent view of computation modules over prescribed time intervals, called 'epochs'. Application-level control of the asynchrony and timing of information flow between various computation modules is realized. The invention has applications which include sensor fusion and network gaming.

Method and apparatus for timing information flow in a distributed system

A method and apparatus is disclosed which provides improved security in distributed-environment voting. At least three voting processors running a voting algorithm are connected to a local area network (LAN) and exchange their individually determined results of a process application. Each result is committed to an interface module where it is checked, authenticated and buffered. The allotted time for receiving and buffering committed results is constrained by a first timed interval within the interface module. The first timed interval may be reset several times. The allotted time for checking and comparing the committed results from each processor is constrained by a second timed interval within each voting processor. A majority vote of those authenticated committed results is formed once all necessary iterations of the both the first and second timed intervals are completed. Enhanced security is thereby afforded to the overall voting process and yields a majority vote that is correct despite the introduction of errors associated with faulty or hostile processors.

Method and apparatus for improved security in distributed-environment voting

Apparatus and method to reduce the duration of timeout periods in fault-tolerant distributed computer systems. When nodes execute a task redundantly and communicate their results over a network for further processing, it is customary to calculate timeouts on a worst-case basis, thereby prolonging their duration unnecessarily. By applying Tchebychev's inequality, which holds for any statistical distribution, to adaptively determine the distribution of the arrival times of the results at the point where further processing of those results takes place, the duration of timeouts is reduced. Successively refining the statistical distribution of the arrival times leads to an improved forecast of future arrivals. Thus timeouts are kept to a minimum without compromising the reliability of the system.

Apparatus and method for reducing duration of timeout periods in fault-tolerant distributed computer systems

Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ('FPGA'). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote. The FPGA engine's flexibility extends to allowing for multiprocessing among the modules where the FPGA engine supports message passing. Implementing these functions in hardware instead of software makes them execute faster. The FPGA is reprogrammable, and only the functions required immediately need be implemented. Inactive functions are stored externally in a Read-Only Memory (ROM). The dynamically reconfigurable FPGA gives the fault-tolerant system an output stage that offers low gate complexity by storing the unused 'gates' as configuration code in ROM. Lower gate complexity translates to a highly reliable output stage, prerequisite to a fault tolerant system.

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Whitesboro, NY, United States of America

Kevin Anthony Kwiat