Advanced Micro Devices Corporation

Hewlett-packard Development Company, L.p.

Kevin Altair Hurd

Jay E Fleischman

Michael Estlick

Kelvin Domnic Goveas

Scott Hilker

Mark M Gibson

Brian M Lay

Daryl Lieu

Weifeng Li

Scott A Hilker

A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.

Single cycle instruction pipeline scheduling

In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. The new operation is independent of other pending operations and therefore can be executed without waiting for execution of other operations, thus reducing execution latency.

Technique for translating dependent instructions

Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.

Processor with increased efficiency via early instruction completion

Methods and apparatus are provided for implementing the advanced encryption standard. The apparatus comprises a first multiplexer receiving during a first cycle a data word, a substitution transformation of the data word and inverse substitution transformation of the data word to provide a first output. During the next cycle, a second multiplexer receives the first output, a mixed column transformation of the first output and an inverse mixed column transformation of the first output to provide a second output. Also in the next cycle, the second output is added to a round key to provide one round of an encoded or decoded digital word compliant with the advanced encryption standard with cycle-by-cycle throughput. The method comprises shifting a received data word and processing the shifted data word using a substitution transformation (encoding) or an inverse substitution transformation (decoding) during a first cycle in an advanced encryption standard unit of a processor. In the next cycle, the result from the first cycle is processed using a mixed column transformation (encoding) or an inverse mixed column transformation (decoding) and the result is added to a round key to provide one round compliant with the advanced encryption with cycle-by-cycle throughput.

Processor with architecture implementing the advanced encryption standard

Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.

Processor with power control via instruction issuance

An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive '1' bits beginning with the least significant bit and whose remaining bits have a value of '0', where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.

Method for floating point round to integer operation

Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.

Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor

Systems and methods for controlling instruction throughput are disclosed. One embodiment of a system may comprise a comparator that determines a difference value in an actual instructions per clock cycle throughput and a target instructions per clock cycle throughput setting, and a throttle control that sums a plurality of difference values to determine an average difference value over a plurality of clock cycles and adjusts the actual instructions per clock cycle throughput based on the average difference value.

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Fort Collins, CO, United States of America

Kevin Altair Hurd