Altera Corporation

Other

Quickturn Design Systems, Inc.

Quickturn Design

Kevin A Norman

Rakesh H Patel

Stephen Paul Sample

Michael R Butts

Chao Chiang Chen

Kunio Nishiwaki

Wilson Wong

Kerry S Veenstra

John E Turner

Thomas Henry White

James D Sansbury

Alan Louis Herrmann

Sau-Ching Wong

Kamlapati Khalsa

Hock-Chuen So

Matthew C Hendricks

Behzad Nouban

Robert J Frankovich

A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

Sample and load scheme for observability internal nodes in a PLD

A programmable logic device architecture. This programmable logic architecture includes a first logic block () containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (), which interfaces with the first logic block (), for performing JTAG functions, configuring the first logic block (), initializing the first logic block (), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block () may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (). The first logic block () includes a plurality of second logic blocks () which may be programmably coupled using a second programmable interconnect network (). The second programmable interconnect network () may be programmably coupled to the first programmable interconnect network (). Furthermore, the plurality of second logic blocks () include a plurality of third logic blocks () which may be programmably coupled using a third programmable interconnect network (). A signal from a third logic block () may be programmably coupled to the other logic blocks, the diagnostic block interface (), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

High-performance programmable logic architecture

A programmable logic device architecture. This programmable logic architecture includes a first logic block ( ) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface ( ), which interfaces with the first logic block ( ), for performing JTAG functions, configuring the first logic block ( ), initializing the first logic block ( ), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block ( ) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network ( ). The first logic block ( ) includes a plurality of second logic blocks ( ) which may be programmably coupled using a second programmable interconnect network ( ). The second programmable interconnect network ( ) may be programmably coupled to the first programmable interconnect network ( ). Furthermore, the plurality of second logic blocks ( ) include a plurality of third logic blocks ( ) which may be programmably coupled using a third programmable interconnect network ( ). A signal from a third logic block ( ) may be programmably coupled to the other logic blocks, the diagnostic block interface ( ), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

PLD with on-chip memory having a shadow register

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (&ldquo;FPGA&rdquo;), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

FPGA with on-chip multiport memory

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (&ldquo;FPGA&rdquo;), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

I/O buffer circuit with pin multiplexing

An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.

Input/output buffer with overcurrent protection circuit

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (&ldquo;FPGA&rdquo;), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

Programmable logic device with multi-port memory

A logic element for a programmable logic device. The logic element includes a look-up table (,) for implementing logical functions, a programmable delay block (,), a storage block (,) configurable as a latch or a flip-flop, and a diagnostic shadow latch (,). A plurality of inputs (,) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (,).

Look-up table based logic element with complete permutability of the inputs to the secondary signals

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ('FPGA'), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ('FPGA'), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.

Growing community of inventors

Belmont, CA, United States of America

Kevin A Norman