International Business Machines Corporation

Kevin A Duncan

William R Tonti

Steven H Voldman

Tad Jeffrey Wilder

Ciaran J Brennan

Toshiharu Saitoh

Gerry Ashton

Terry D Keim

A shift register latch (SRL) () compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (). The SRL includes a master latch (), a slave latch () and a circuit element () connected between the scan clock tree and the master latch. The scan clock generates a clock signal () having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (') based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention

LSSD-compatible edge-triggered shift register latch

In order to divert damaging currents into an electrostatic discharge (ESD) protection device during an ESD event, a tungsten wire resistor is incorporated into a current path connected in parallel with the ESD protection circuitry. The tungsten wire resistor has linear current-voltage (IV) characteristics at low currents, and non-linear IV characteristics at high current levels. The width and length of the resistor is chosen so that the resistor experiences significant self-heating caused by the higher currents generated by the ESD event. At a higher current level, the resistor becomes hot and its resistance increases dramatically. As a result the voltage drop across it increases thus diverting excess current into the parallel connected ESD protection circuitry. This limits the current through the resistor and thereby protects circuit elements in series with the resistor.

Tungsten hot wire current limiter for ESD protection

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Milton, VT, United States of America

Kevin A Duncan