International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Kevin A Batson

Robert E Busch

Rajiv V Joshi

Robert Maurice Houle

Robert Anthony Ross, Jr

Fred John Towler

Gary S Koch

Garrett Stephen Koch

Reid A Wistort

Robert Louis Franch

Geordie M Braceras

Sebastian Theodore Ventrone

John Atkinson Fifield

Albert Manhee Chu

George Maria Braceras

K Paul Muller

Darren Lane Anand

Eric D Hunt-Schroeder

Michael J Lee

Ezra D B Hall

Robert Dean Adams

Devesh Dwivedi

Siva Kumar Chinthu

Suresh Pasupula

The present disclosure relates to semiconductor structures and, more particularly, to a LDO regulator circuit and methods of manufacture. The structure includes a comparator connected to a first transistor of a low drop-out (LDO) circuit; a second transistor connected to the first transistor; and a feedback loop connected to the first transistor and an output of the LDO circuit.

Low drop-out (LDO) regulator circuit

Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

Voltage-aware adaptive static random access memory (SRAM) write assist circuit

A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

Method and apparatus for calibrating internal pulses in an integrated circuit

A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Programmable pulsewidth and delay generating circuit for integrated circuits

A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

Alignment insensitive D-cache cell

An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.

Memory device with data line steering and bitline redundancy

The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.

Redundant array architecture for word replacement in CAM

A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)

A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

High reliability content-addressable memory using shadow content-addressable memory

A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0.2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.

System and method for conserving power in a content addressable memory by providing an independent search line voltage

A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a &ldquo;hidden&rdquo; refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.

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Williston, VT, United States of America

Kevin A Batson