Intel Corporation

Kevan A Lillie

Adee Ofir Ran

Itamar Fredi Levin

Amir Laufer

Kent C Lusted

Assaf Benhamou

Itay Tamir

Shlomi Lalush

Yaakov Dalsace

Richard I Mellitz

Mingming Xu

David L Chalupsky

Tomer Fael

Nishantkumar Shah

David Golodni

Dima Hammed

Elior Segev

Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Component firmware interaction using hardware registers

Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.

Technologies for cooperative link equalization without disruption to link traffic

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

Signal detection techniques using clock data recovery

Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

Ethernet auto-negotiation with parallel detect for 10G DAC or other non-auto-negotiated modes

Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.

Techniques for testing receiver operation

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Chandler, AZ, United States of America

Kevan A Lillie