International Business Machines Corporation

Globalfoundries Inc.

Keunwoo Kim

Ching-Te Kent Chuang

Rajiv V Joshi

Jente Benedict Kuang

Jae-Joon Kim

Kevin John Nowka

Rouwaida N Kanj

Hung Cai Ngo

Vinod Ramadurai

Edward J Nowak

Richard Quimby Williams

Fadi Hikmat Gebara

Meng-Hsueh Chiang

Tong Li

Koushik Kumar Das

Soojae Park

Ching Te Chuang

A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.

Circuit-level abstraction of multigate devices using two-dimensional technology computer aided design

A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors

A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Fet-bounding for fast TCAD-based variation modeling

FET-bounding for fast TCAD-based variation modeling

A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

FinFET-based boosting supply voltage circuit and method

Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices

In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.

Table-lookup-based models for yield analysis acceleration

Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.

Table lookup method for physics based models for SPICE-like simulators

A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.

Technology computer-aided design (TCAD)-based virtual fabrication

A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

Structure for high density stable static random access memory

Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations.

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Somers, NY, United States of America

Keunwoo Kim