Qualcomm Incorporated

Keunsoo Roh

Hee Jun Park

Haw-Jing Lo

Mosaddiq Saifuddin

Pratik Patel

SankaraRao Kunapareddy

Jeremy Haugen

Chun Xiang He

Nicholas Ambur

In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

Controlling a refresh mode of a dynamic random access memory (DRAM) die

Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

Systems and methods for dynamically adjusting memory state transition timers

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San Diego, CA, United States of America

Keunsoo Roh