Leadis Technology, Inc.

Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Keunmyung Lee

Norman H Chang

Sung Tae Ahn

Osamu Samuel Nakagawa

Shen Lin

Weize Xie

Soo-Young Oh

Hannsjorg Obermaier

Chang Oon Kim

Chan Young Jeong

Tae Kwang Park

Yung Jin Jeon

Tae-Kwang Park

Dae Young Ahn

Keh-Jeng Chang

Yoshio Nishi

A single-chip column driver for organic light emitting diode (OLED) display is disclosed. Instead of using two column drivers for dual scan, the present invention uses one column driver driving both the upper and the lower OLED panels. The column driver has a two set of output circuitry: one for driving the upper panel and the other for driving the lower panel. The single chip solution of the present invention eliminates the problem of display uniformity without increasing the part count. The invention also enables independent control of RGB without further increasing the part count.

Column driver for OLED display

A single scan driver for an organic light emitting diode (OLED) display is disclosed, that can reduce the required power consumption. By connecting together both ends of each column line so that a single driver circuit can drive both ends of each column line together, the column line resistance is reduced, resulting in a significant reduction in power consumption.

Single-scan driver for OLED display

A scheme to reduce output variations in a column driver for a flat-panel display by sharing the characteristics of analog circuit is disclosed. An input multiplexer is provided between two neighboring digital inputs, and an output multiplexer is provided between two neighboring analog outputs so that the characteristics of neighboring analog circuits can be shared by multiplexing. The averaging effect by sharing reduces variations in the output. The multiplexing may be done either in time division or on a frame-by-frame basis.

Method and apparatus for reducing output variation by sharing analog circuit characteristics

A driver for driving an STN LCD is disclosed. A preferred embodiment comprises a 3-line output display data for storing display data, an XOR block for finding mismatches between each 3-line output set of the stored display and orthogonal function signals, a decoder block for calculating mismatch numbers, a level shifter block for shifting the data level of the mismatch numbers to another level, and a voltage selector block for selecting a voltage level from 2 levels of voltage. Because data latches and output latches are not necessary, the driver of the present invention achieves significant reduction in the circuit components and chip size without compromising the display quality.

Method and apparatus for driving STN LCD

A signal equalization system provides a block-mode equalization system for digital equalization in computer and networking systems in which a &ldquo;1&rdquo; bit pulse is followed by a significant negative bit and less significant negative bit pulses as a multiple groups with a lower bit rate. The magnitude of the grouped bit pulses, or blocks of equalization bit pulses, can be the average value of the individual bits to produce a clean output waveform. Since the block compensates for the lower frequency response of the channel, its effectiveness is not sensitive to the exact location of the pulses. This makes it possible to align the blocks in wide pulses having decreasing magnitudes and increasing durations. This further means that when data multiplexing is involved in driver circuitry for the signal transmitter, the block can be generated from a lower frequency clocked domain before the multiplexing without burdening the high frequency side of the driver circuitry.

Block-mode equalization for data communications

A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Parallel push algorithm detecting constraints to minimize clock skew

An electrical interconnection structure. The electrical interconnection structure includes a mother board substrate having a plurality of layers. At least one layer includes a signal path having a characteristic impedance of Z.sub.O and a conductive ground plane. A signal via passes through each layer of the mother board substrate. The signal via electrically is connected to the signal path. A ground via passes through each layer of the mother board substrate. The ground via is electrically connected to the conductive ground plane. The electrical interconnection structure further includes a plurality of flex circuits. Each flex circuit includes a flex signal path having a characteristic impedance of Z.sub.O and a flex ground plane. Each flex signal path is electrically connected to the signal via and each flex ground plane is electrically connected to the ground via. The connections between the flex signal path and the signal via, and between the flex ground plane and the ground via can be permanent or separable.

Minimal length computer backplane

Data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel on-chip and off-chip interconnects. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI, PCB, and MCM interconnects. Four subsystems are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design mode with performance browsing, goal-directed synthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet-style graphical user interface.

Computer-aided design methods and apparatus for multilevel interconnect

A via connection and method for making the same for integrated circuits having multiple layers of electrically conductive interconnect lines separated by an insulative layer. The via connection is characterized by a very thin layer of high resistivity material lining the via hole in conductive contact with interconnect lines in two layers. The resistivity of the thin layer material is in a range from about 10 to about 50 times the interconnect line resistivities and generally has a thickness of less than 100 nanometers. The thin layer assures more uniform current flow in the via connection thereby preventing electromigration, with reduced peak local current density by causing current to swing more widely around the corner at the interface between the interconnect lines at the via.

Growing community of inventors

Palo Alto, CA, United States of America

Keunmyung Lee