Samsung Electronics Co., Ltd.

Keunhee Bai

Yongho Jeon

Sekoo Kang

Dongseok Lee

Heonjong Shin

Jinhong Park

Jinseok Heo

Seungseok Ha

Eunsil Park

Seungmin Lee

Sanghyun Lee

Seunghoon Park

Jongchul Park

Sungyeol Kim

Dohyoung Kim

Dongchan Kim

Sungho Jang

Sunhom Steve Paak

Injae Lee

Young-Ju Park

Doo-Young Lee

Hak-Sun Lee

Heungsik Park

Dongho Cha

Gyungjin Min

Sungwoo Myung

Hyuck Shin

Kisoo Chang

Seongchul Hong

Minjoon Park

Kyoung Hwan Yeo

Kyounghwan Yeo

Heeyoung Go

Johnsoo Kim

Suntaek Lim

Sae Il Son

Seungjun Kim

Seungju Park

Cheolin Jang

Hyunki Lee

Duck-Nam Kim

Kwang-Ho You

A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction.

Semiconductor device including gate structure and separation structure

A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.

Methods of manufacturing semiconductor devices

Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.

Fabrication system of semiconductor device and method of fabricating a semiconductor device using the same

An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.

Integrated circuit device having a work function control layer with a step portion located on an element isolation layer

An extreme ultraviolet exposure system includes an exposure chamber having an internal space, upper and lower electrostatic chucks, a power supply, a light source, and a mask. The upper electrostatic chuck includes first and second electrodes that are adjacent to one another and that generate an electric field of different polarities, respectively, to provide an electrostatic force. The mask is attachable to the lower surface of the upper electrostatic chuck by the electrostatic force. The mask has a metal thin film pattern including a first region in which a metal thin film that shields the electric field, and a second region in which the metal thin film is not disposed and through which the electric field is transmitted. When the mask is attached, the electric field transmitted through the second region applies an attractive force or a repulsive force to charged particles in the exposure chamber.

Extreme ultraviolet exposure system

An extreme ultraviolet (EUV) exposure apparatus includes a chamber, an EUV source in the chamber and configured to generate an EUV beam, an optical system above the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a plasma source configured to provide plasma to the reticle to electrically neutralize the reticle charged by the EUV beam.

Extreme ultraviolet (EUV) exposure apparatus and method of manufacturing semiconductor device using the same

A method for forming a fine pattern includes forming line patterns and a connection pattern on a semiconductor substrate, the line patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the connection pattern connecting portions of the line patterns adjacent to each other in the second direction, and performing an ion beam etching process on the connection pattern. The ion beam etching process provides an ion beam in an incident direction parallel to a plane defined by the first direction and a third direction perpendicular to a top surface of the semiconductor substrate, and the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

Method for forming a fine pattern

Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.

Semiconductor devices and methods of manufacturing the same

A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

Methods of forming semiconductor device

Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.

Semiconductor devices including a gate core and a fin active core and methods of fabricating the same

Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Methods of forming semiconductor devices using hard masks

Growing community of inventors

Suwon-si, South Korea

Keunhee Bai