Hynix Semiconductor Inc.

Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Other

Keun Woo Lee

Ki Seog Kim

Sung Kee Park

Keon Soo Shim

Yoo Nam Jeon

Sung Yeol Park

Jin Hyock Kim

Young Seok Kwon

Jin Gwan Shin

Sang Hoan Chang

Ki Jun Kim

Susan H Hardin

Young Seon You

You Min Ji

Mitsu Reddy

Nasanshargal Battulga

Michael A Rea

Brent Mulder

Chris Hebel

Alok Bandekar

Anelia Kraltcheva

Ivan Pan

Costa M Colbert

Andrei Volkov

Bong Kil Kim

Yong Joo Shim

Chang Sub Jeon

A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Memory controller and operating method thereof

A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

Method and system for providing quiz together with advertisement in instant message service (IMS) chat room

An operating method of a data storage device includes setting a first page access unit using a first page electrically coupled with a first word line of a first plane and a second page electrically coupled with a second word line of a second plane; and setting a second page access unit using a third page electrically coupled with a second word line of the first plane and a fourth page electrically coupled with a first word line of the second plane.

Data storage device and operating method thereof

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a Schottky junction. The barrier metal layer includes a first nitride material, in which a first material is nitrified, and a second nitride material, in which a second material is nitrified. The barrier metal layer is formed of a mixture of the first nitride material and the second nitride material. At least one of the first material or the second material is rich in a metal used to form the first nitride material or the second nitride material.

Semiconductor device and method of fabricating the same

A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.

Phase change random access memory and method for manufacturing the same

A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area.

Phase-change memory device and method of fabricating the same

A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated.

Flash memory device and method of operating the same

A memory cell array in a semiconductor device includes a semiconductor substrate having active areas and isolation areas in parallel, a plurality of select lines having generally a U like shape and is configured to cross over the active areas and the isolation areas, and a plurality of word lines formed between the select lines. In view of the select line being formed in U like shape, an occurrence of a punch through phenomenon is prevented by a junction area formed between the select lines. As a result, a margin for reducing a width of the select line is increased.

Memory cell array in a semiconductor memory device with select lines formed in a U-like shape

A method to be implemented on or in a computer is disclosed, where the method includes data collection, calibration, candidate selection, and analysis of data streams associated with each candidate to classify single molecule fluorescence resonance energy transfer events. Once classified, the classification can be related to the nature of the events, such as the identification of dNTP incorporation during primer extension to obtain a base read out of an unknown template.

Method for analyzing dynamic detectable events at the single molecule level

Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a node between a flash memory cell and the string select transistor or the source select transistor.

Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell

A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel region is set greater than a predetermined value. Therefore, an electric field applied between the control gate and the channel region upon cycling can be mitigated. As a result, a data retention characteristic and an endurance characteristic can be improved.

Flash memory device

A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below the control gate line. An island conductive line is formed between the first and second floating gates and within the isolation films. The island conductive line extends along the first direction and is configured to receive a voltage in order to prevent interference between the first and second floating gates.

Flash memory device and method of manufacturing the same

A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.

Row decoder in flash memory and erase method of flash memory cell using the same

Provided is concerned with a method of erasing a NAND flash memory device, capable of restraining an erasing disturbance fail arising from a deselected cell block and improving a product yield of the device by applying a negative voltage to a well of a high voltage transistor forming an X-decoder during an erasing operation in the NAND flash memory device.

Method of erasing NAND flash memory device

A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.

Growing community of inventors

Kyungki-do, South Korea

Keun Woo Lee