Skhynix Inc.

Hynix Semiconductor Inc.

Keun-Soo Song

Young-Ju Kim

Dong-Uk Lee

Kwan-Weon Kim

Nak-Kyu Park

Seung-Wook Kwak

Sang-Hoon Shin

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Semiconductor integrated circuit including master chip and slave chip that are stacked

Semiconductor integrated circuit

This technology relates to a semiconductor system. The semiconductor system may include a first semiconductor device capable of outputting a clock signal, a data strobe signal, and data; and a second semiconductor device capable of generating a division enable signal and a data input clock signal in response to the clock signal when performing a write operation, generating an internal strobe signal by dividing the data strobe signal in response to the division enable signal, and aligning the data in response to the internal strobe signal, wherein the first semiconductor device receives the division enable signal from the second semiconductor device and trains the data strobe signal so that the data strobe signal is output in a predetermined section.

Semiconductor system and method of performing write leveling operation thereof

Semiconductor integrated circuit including at least one master chip and at least one slave chip

Semiconductor integrated circuit with stack package structure

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.

Stack bank type semiconductor memory apparatus capable of improving alignment margin

A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the edge area.

Semiconductor integrated circuit including column redundancy fuse block

A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.

Fuse circuit and driving method thereof

A PLL is provided with an optimum operating point in order to have appropriately a frequency margin and a locking time. There is provided a phase looked loop which includes: a frequency divider for dividing an output signal by a dividing integer corresponding to an input code; an encoding unit for encoding the input code to generate an encoded code; and a loop filtering unit configured to adjust elements in response to the encoded code.

Growing community of inventors

Gyeonggi-do, South Korea

Keun-Soo Song