Skhynix Inc.

Keun Soo Song

Woo Yeol Shin

Woongrae Kim

Bok Rim Ko

Sang Hoon Shin

Seung Wook Kwak

Nak Kyu Park

Hae Kang Jung

Sang Kwon Lee

Dong Kyun Kim

Hyeng Ouk Lee

Jong Joo Shim

Hongjoo Song

A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Semiconductor apparatus for compensating for degradation and semiconductor system using the same

A semiconductor package for performing a reset operation includes a first semiconductor device including a first resistor element coupled to a reset pin, the first semiconductor device configured to be applied with a reset signal through the reset pin such that the reset operation is performed. The semiconductor package includes a second semiconductor device including a second resistor element coupled to the reset pin, the second semiconductor device configured to be applied with the reset signal through the reset pin such that the reset operation is performed. The first resistor element and the second resistor element may be selectively coupled to the reset pin when the reset operation is performed.

Semiconductor package and semiconductor system related to performing a reset operation

A semiconductor system includes a first semiconductor device configured to output a clock signal, a strobe signal and mode information signals, and detect a phase difference of the clock signal and the strobe signal depending on a detection signal. The semiconductor system may include a second semiconductor device configured to generate the detection signal by comparing phases of the clock signal and the strobe signal.

Semiconductor system

A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

Interface circuit for high speed communication, and system including the same

A semiconductor system may include a controller configured to provide a command clock and a control signal to a semiconductor memory device, and the semiconductor memory device configured to transmit/receive external data and a plurality of data clocks to/from the controller, wherein the plurality of data clocks comprise a first read data strobe signal and a second read data strobe signal, and the semiconductor memory device transmits both of the first read data strobe signal and the second read data strobe signal to the controller or transmits one of the first read data strobe signal and the second read data strobe signal to the controller, based on an operation select signal.

A semiconductor system may include a controller configured to provide a first external clock and a control signal to a semiconductor device, and the semiconductor device configured to transmit/receive external data and a plurality of second external clocks to/from the controller, wherein the plurality of second external clocks comprise a third primary external clock and a third secondary external clock, and the semiconductor device transmits both of the third primary external clock and the third secondary external clock to the controller or transmits one of the third primary external clock and the third secondary external clock to the controller, based on an operation select signal.

A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.

A semiconductor system may include a first semiconductor apparatus, and a second semiconductor apparatus. The first semiconductor apparatus may be configured to transmit a first system clock signal and a second system clock signal having a first frequency, and transmit a data strobe signal having a second frequency. The second semiconductor apparatus may include a clock multiplier configured to generate a read data strobe signal having the second frequency, based on the first and second system clock signals.

Semiconductor apparatus, semiconductor system, and system relating to dual clock transmission

A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. The second and third pads may receive a second external voltage. The second pad may provide the second voltage, and the third pad may provide the third voltage.

Memory apparatus using plurality of power sources and system including the same

A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system.

Interface circuit for high speed communication and system including the same

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.

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Icheon-si, South Korea

Keun Soo Song