Skhynix Inc.

Keun Seon Ahn

Jin Ha Hwang

Yo Han Jeong

Eun Ji Choi

Kwan Su Shon

Soon Sung An

Sung Hwa Ok

Jae Hyeong Hong

Jun Seo Jang

Min Su Kim

Sun Ki Cho

Kyeong Min Chae

In Seok Kong

Bon Kwang Koo

Jae Hoon Jung

Dae Ho Yang

Jun Sun Hwang

Dong Wook Jang

Heon Ki Kim

Gwan Woo Kim

Beom Kyu Seo

Su Han Lee

Jung Yeop Lee

Ji Young Lee

A receiver circuit includes an input unit configured to receive a reception pattern signal in a training mode, and a reception normal signal in a normal mode, an enable control unit configured to determine whether to activate an enable signal according to the reception pattern signal in the training mode, a first decision feedback equalizer configured to operate in an activation period of the enable signal, and to remove a first post-cursor component for the reception normal signal by calibrating a currently received value based on a previously received value of the reception normal signal, and a second decision feedback equalizer configured to, when the enable signal is in an activated state, remove second to Npost-cursor components for the reception normal signal by adjusting driving abilities of input transistors, to which the currently received value is applied, according to patterns of the reception normal signal.

Receiver circuit and operation method for the same

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Pre-charge control circuit and voltage generation circuit including the same

A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Duty cycle correction circuit and method of operating the same

The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit

A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

Data input buffer and semiconductor apparatus including the same

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Impedance calibration circuit and semiconductor apparatus including the same

Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.

Calibration circuit and operating method of the calibration circuit

A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.

Data output buffer

The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

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Seoul, South Korea

Keun Seon Ahn