Hynix Semiconductor Inc.

Skhynix Inc.

Keun Kook Kim

Bok Rim Ko

Kwang Soon Kim

Kwang Jun Cho

A semiconductor device includes a control circuit configured to generate an input enable signal, an output enable signal, a latch control signal, and an error correction control signal based on a write control signal, a write check command, and a read check command for performing an error correction test mode; a latch circuit configured to generate latch data, a latch parity, and a latch masking signal by latching input data, an input parity, and an input masking signal and configured to re-store corrected data as the latch data, during a period in which the latch control signal is enabled; and an error correction circuit configured to generate the corrected data by correcting an error, included in the latch data, based on the latch data, the latch parity and the latch masking signal during a period in which the error correction control signal is enabled.

Semiconductor device and semiconductor system for testing error correction circuit

An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal.

Internal voltage generation circuit

A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption.

Semiconductor memory device

A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled.

Refresh method and semiconductor memory device using the same

There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Command generation circuit and semiconductor memory device

A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal.

A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.

Fuse circuit with ensured fuse cut status

A driving controller for use in stabilizing transient voltages from power supplies is presented. The driving controller includes a first pulse generator, a second pulse generator, and a control signal generator. The first pulse generator is configured to generate a power-up pulse signal including a pulse activating at a time of terminating a power-up period. The second pulse generator is configured to generate a detection pulse signal including a pulse that is being active from a time when an internal voltage reaches a predetermined level. The control signal generator is configured to generate an operation control signal, which controls a driving controller activating the internal voltage, in response to the power-up pulse signal and the detection pulse signal.

Driving controller and internal voltage generation circuit

There is provided a flag signal generation circuit. The flag signal generation circuit includes a status register read (SRR) signal generating unit receiving an idle signal and an SRR command to generate an SRR signal; a pulse signal generating unit receiving an SRR signal to generate a pulse signal; and a flag signal generating unit receiving the pulse signal and a read signal for SRR to generate a flag signal.

Flag signal generation circuit and semiconductor memory device

A pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

Pad input signal processing circuit

A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated.

Data bus sense amplifier circuit

A driving device using a CMOS inverter performs a stable operation by using a compensating circuit to compensate variation widths when the process condition or external environment is changed. The driving device comprises a power regulating unit for regulating a driving voltage level depending on characteristics of a MOS transistor and a delay unit comprising a plurality of CMOS inverters driven by the driving voltage regulated by the power regulating unit.

Driving device using CMOS inverter

A counter control signal generating circuit is disclosed. The circuit includes a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address, a second counter for counting the first counted address for a second latency, thereby generating a second counted address, a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the second counter, in response to the write recognition signal, a first detecting signal generator configured to receive the write recognition signal, generate a first command signal obtained after counting of the write recognition signal for the first latency, and generate a first detecting signal, which is enabled in response to the write recognition signal, and a second detecting signal generator configured to receive the first command signal, generate a second command signal obtained after counting of the first command signal for the second latency, and generate a second detecting signal, which is enabled in response to the first command signal.

Counter control signal generating circuit

A pumping circuit of a semiconductor device includes a power supply unit for supplying a power source voltage to a first node, a first transfer pump for transferring a first electric potential of the first node to a second node, a first pumping unit coupled to the first node for pumping the power source voltage applied to the first node, a first pump control unit for controlling a voltage applied to a gate of the first transfer pump, a second transfer pump for transferring a second electric potential of the second node to a high voltage output terminal, a second pumping unit coupled to the second node for selectively pumping the second electric potential of the second node, and a second pump control unit for controlling a voltage applied to a gate of the second transfer pump in response to the power source voltage level. If the power source voltage is higher than a predetermined voltage, the first pumping unit performs a pumping operation, and the second pumping unit performs only an on or off operation.

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Seoul, South Korea

Keun Kook Kim