Samsung Electronics Co., Ltd.

Other

Psm Inc.

Keun-Ho Lee

Young-Tae Kim

Young-Nam Hwang

Tai-Kyung Kim

Ui-hui Kwon

Young-Kwan Park

Chang-Sub Lee

Chang-Hoon Choi

Dae-Sin Kim

Won-Young Chung

Seon-Young Lee

Sang-Woo Oh

Choong-Ho Lee

Dong-won Kim

Young-Gu Kim

Seung-Chul Lee

Sun-Yong Choi

Nak-jin Son

Byung-Yong Choi

Min-Chul Park

Je-Hyun Lee

Chang-wook Jeong

Jong-Chol Kim

Je-Dal Jeon

Jong-wook Jeon

Won-young Chung

Moon-Hyun Cho

In-Seog Chung

Seung-Hyun Song

Kee-Hyun Paik

Olivier Postel

Kwang-Seok Lee

Hyo-Eun Park

Jeong-Hoon Ko

Vasily Zabelin

Jeong-Ho Lyu

Sachio Nagura

Myung-Jin Park

The present disclosure relates to a cold plasma generating apparatus that can efficiently ignite (initially discharge) cold plasma and easily match common impedance and that is optimized for use in applications related to sterilization because it can uniformly distribute power to multiple plasma sources through a single power supply in a multi-plasma array configuration and increase effective plasma volume, and a multi-cold plasma array apparatus comprising the same.

Cold plasma generating apparatus and multi-cold plasma array apparatus comprising the same

Provided is a hand-type low temperature microwave plasma generator that is configured to implement plasma even in a low power state, and be easily applied to various small devices using microwave plasma including medical treatment and the like of wound treatment or cell treatment.

Hand-type low temperature microwave plasma generator

A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.

Circuit design method and simulation method based on random telegraph signal noise

A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.

Method of measuring thickness, method of processing image and electronic system performing the same

A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.

System for simulating semiconductor device and related method of operation

A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

Semiconductor devices including an air-gap and methods of manufacturing the same

Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Method for fabricating semiconductor device

A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.

Nonvolatile memory devices and methods of forming the same

In a method of forming a phase-change memory device, a variable resistance member may be formed on a s semiconductor substrate having a contact region, and a first electrode may be formed to contact a first portion of the variable resistance member and to be electrically connected to the contact region. A second electrode may be formed so as to contact a second portion of the variable resistance member.

Phase-change memory device and method of manufacturing the same

In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.

Image sensor having 3-dimensional transfer transistor and its method of manufacture

In one aspect, a memory device is provided which includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction, an array of programmable volumes electrically connected between the bit lines and word lines, and thermally conductive striped patterns located between the programmable volumes of the array and extending in at least one of the first and second directions.

Memory device including thermal conductor located between programmable volumes

Disclosed herein are an apparatus and method for manufacturing a balloon catheter in which a non-contact type laser perforator and printer are separately provided above a primary extruder such that inflation apertures can be uniformly perforated through a non-vulcanized lumen tube and simultaneously, tube cutting positions can be printed on the lumen tube at positions uniformly spaced apart from the inflation apertures without stopping a primary extrusion process. Also, a bond preventing agent layer is coated on the lumen tube at balloon inflating portions prior to cutting the tube, to facilitate a secondary extrusion of the tube. With this configuration, continuous and accurate perforation of inflation apertures is possible and automatic tube cutting can be achieved based on the printed tube cutting positions. Also, the present invention can compensate for a time delay due to a bond preventing agent application process and achieve high productivity and minimized loss of material.

Apparatus for manufacturing balloon catheter and method the same

A phase-change memory device may include first and second spaced apart conductive electrodes, and a phase-change memory element coupled between the first and second conductive electrodes. More particularly, a first portion of the phase-change memory element may have a first cross-sectional area along a current path between the first and second conductive electrodes, and a second portion of the phase-change memory element may have a second cross-sectional area along the current path between the first and second conductive electrodes. Moreover, the first and second cross-sectional areas may be different.

Phase change memory devices including memory elements having variable cross-sectional areas

Growing community of inventors

Seoul, South Korea

Keun-Ho Lee