Samsung Electronics Co., Ltd.

Keun-Hee Bai

Do-hyoung Kim

Bo-un Yoon

Kyoung-hwan Yeo

Sang-Jine Park

Kee-Sang Kwon

Yong-Ho Jeon

Kwang-Yong Yang

Myeong-Cheol Kim

Yong-jin Kim

Jin-wook Lee

Kyeong-Koo Chi

Chang-Jin Kang

Kwan-heum Lee

Seung-mo Ha

Cheol-Kyu Lee

Dong-hoon Khang

Yoon-Jae Kim

Sang-Hyun Lee

Dong-Seok Lee

Hyo-San Lee

Yong-Jin Kim

Sang-Kuk Kim

Chul-Ho Shin

Sung-woo Kang

Ha-Young Jeon

Ken Tokashiki

Young-Mook Oh

Seung-Seok Ha

Shin-hye Kim

Hak-yoon Ahn

Seong-han Oh

A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.

Semiconductor device

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Method of manufacturing semiconductor device having stressor

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Semiconductor devices including a dummy gate structure on a fin

Semiconductor device having stressor and method of manufacturing the same

Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

Semiconductor devices including insulating gates and methods for fabricating the same

A fabricating method of a semiconductor device includes forming an interlayer insulation layer on a substrate, the interlayer insulation layer including a storage node contact plug, forming an etch stop layer on the interlayer insulation layer, the etch stop layer including a silicon layer or a silicon germanium layer, forming a molding insulation layer on the etch stop layer, forming a hole in the molding insulation layer by selectively etching the molding insulation layer until a portion of the etch stop layer is exposed, forming a first conductive layer conformally on an inner surface of the hole and on a top surface of the molding insulation layer, and forming a metal silicide pattern in a predetermined area of the etch stop layer exposed by the molding insulation layer by annealing the first conductive layer and the etch stop layer.

Fabricating method of semiconductor device

A method of processing a substrate using plasma includes loading a substrate into a chamber, processing the substrate with a first plasma mode and then processing the substrate with a second plasma mode, wherein at least one of the first plasma mode and the second plasma mode is a time-modulation mode in which a plasma induced in the chamber is periodically turned on and off to reduce plasma-induced damage in the substrate.

Method of processing a substrate

In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Method of forming semiconductor cell structure, method of forming semiconductor device including the semiconductor cell structure, and method of forming semiconductor module including the semiconductor device

A pulse plasma matching system includes an RF matching box configured to receive an RF power pulse generated by an RF power source, configured to perform a plasma impedance matching, and configured to apply the RF power pulse to a process chamber, and a network analyzer configured to measure an impedance of plasma generated in a process chamber. A controller is configured to generate a capacitance control signal corresponding to a plasma impedance value measured by the network analyzer, configured to supply the capacitance control signal to the RF matching box, and configured to generate an impedance matching compensation pulse, and a phase shifter is configured to receive the impedance matching compensation pulse and to shift a phase of the impedance matching compensation pulse to synchronize the impedance matching compensation pulse to the RF power pulse.

Pulse plasma matching systems and methods including impedance matching compensation

There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (SiGe) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same

Provided are methods and systems for monitoring a state of a plasma chamber. In the method, an optical characteristic of plasma generated in a plasma chamber including a window is measured in a predetermined measurement wavelength band. A process status index (PSI) is extracted from the measured optical characteristic. A state of the plasma chamber is evaluated by analyzing the extracted PSI. The optical characteristic of the plasma is measured in the predetermined measurement wavelength band in which a transmittance of light passing through the window is substantially independent of a wavelength of the light.

Methods and systems for monitoring state of plasma chamber

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Suwon-si, South Korea

Keun-Hee Bai