Samsung Electronics Co., Ltd.

Keum-Joo Lee

In-Seak Hwang

Young-min Kwon

Chang-Lyoung Song

In-seak Hwang

Tae-Han Kim

Woo-Sung Lee

Man-Sug Kang

Dae-Keun Kang

Jin-Hye Bae

Bo-Wo Choi

A method of fabricating a semiconductor device includes forming a mask pattern on an active region of a substrate defined by an isolation region. The mask pattern includes an opening therein exposing a portion of the active region. The exposed portion of the active region is etched to define a preliminary gate trench therein including opposing sidewalls and a surface therebetween, where portions of the mask pattern extend to edges of the active region outside the preliminary gate trench. An annealing process is performed on the substrate to form a gate trench from the preliminary gate trench, and gate electrode is formed in the gate trench. The preliminary gate trench and the gate trench have a substantially similar width defined between the edges of the active region including the portions of the mask pattern thereon.

Methods of fabricating recessed channel metal oxide semiconductor (MOS) transistors

Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad. A native oxide layer on the exposed pad may be removed by a fourth etching process to form a capacitor contact hole. A conductive layer may be formed in the capacitor contact hole to form a capacitor.

Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same

The present invention provides methods of cleaning a semiconductor device by removing contaminants, such as particles and/or etching by-products, from a structure of a semiconductor device using a first cleaning solution including a mixture of ammonium hydroxide (NHOH), hydrogen peroxide (HO) and deionized (DI) water, and a second cleaning solution including ozone (O) water. The present invention also provides methods of manufacturing a semiconductor device using these methods of cleaning the semiconductor device.

Methods of cleaning a semiconductor device and methods of manufacturing a semiconductor device using the same

An apparatus for drying a wafer includes a rotating chuck configured to rotate the wafer. A movable de-ionized water supply member and an organic solvent supply member are positioned adjacent a face of the wafer. The de-ionized water supply member supplies de-ionized water onto the wafer, and the organic solvent supply member has a plurality of solvent supply nozzles disposed to supply an organic solvent onto the wafer. The organic solvent supply member includes a first solvent supply member and a second solvent supply member. The de-ionized water supply member and the first solvent supply member move radially between a position adjacent the central portion of the wafer and the edge portion of the wafer.

Wafer spin drying apparatus with a plurality of supply nozzles and methods for using the same

A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 &angst;, preferably 200 &angst; from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Growing community of inventors

Hwaseong-si, South Korea

Keum-Joo Lee