Globalfoundries U.S. Inc.

Ketankumar Harishbhai Tailor

Peter Baars

Judson Robert Holt

Viorel C Ontalus

Alexander M Derrickson

Zhixing Zhao

Ruchil Kumar Jain

Michael Zier

Crystal R Kenney

A transistor structure with a multi-layer field plate and related methods are disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a field plate on the thicker portion of the dielectric layer.

Transistor structure with multi-layer field plate and related method

Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Transistor integration on a silicon-on-insulator substrate

A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.

Transistor structure with gate over well boundary and related methods to form same

Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

Bipolar transistor structures with base having varying horizontal width and methods to form same

Disclosed are a semiconductor structure and method of forming the structure. The semiconductor structure includes an extended drain metal oxide semiconductor field effect transistor (EDMOSFET). The EDMOSFET includes, in the semiconductor layer, a body well, which has a source region therein, and a drain drift well, which abuts the body well and has a drain region therein. A trench gate structure is within the drain drift well positioned laterally between the body-drain drift junction and an internal shallow trench isolation (STI) region and the internal STI region is between the trench gate structure and the drain region. A primary gate structure is on the top surface of the semiconductor layer traversing the body-drain drift junction and optionally extending over the trench gate structure. Gate dielectric material physically separates gate conductor materials of the primary and trench gate structures. Optionally, the EDMOSFET includes more than one trench gate structure.

Extended drain field effect transistor with trench gate(s) and method

An integrated circuit (IC) structure and a field plate are disclosed. The IC structure and field plate may find advantageous application with, for example, extended drain metal-oxide semiconductor (EDMOS) transistors. The IC structure includes a transistor including a metal gate structure and a drain extension region extending laterally from partially under the metal gate structure to a drain region. A metal field plate is over the drain extension region. Due to being formed simultaneously as part of a gate-last formation approach, the metal field plate has an upper surface coplanar with an upper surface of the metal gate structure. A field plate contact may be on the metal field plate.

Integrated circuit structure with metal gate and metal field plate having coplanar upper surfaces

Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.

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Dresden, Germany

Ketankumar Harishbhai Tailor