Intel Corporation

Ketan S Bhat

Stephen H Gunther

Gregory Scott Mathews

Robert T Jackson

Borys S Senyk

Eugene P Matter

Dennis Reinhardt

A computer system maintaining cache coherency among a plurality of caching devices coupled across a local bus includes a bus master, a memory, and a plurality of cache complexes, all coupled to the local bus. When the bus master requests a read or write with the memory, the cache complexes snoop the transaction. Each cache complex asserts a busy signal during the snooping process. A detection circuit detects when the busy signals have been de-asserted and asserts a done signal. If one of the snoops results in a cache hit to a dirty line, the respective cache complex asserts a dirty signal. If one of the snoops results in a cache hit to a clean line, the respective cache complex asserts a clean signal. If the memory detects a simultaneous assertion of the dirty signal and the done signal, it halts the transaction request from the bus master.

Multi-processing cache coherency protocol on a local bus

A power control circuit and corresponding technique for reducing power consumption by an electronic device and thereby increasing performance. The power control circuit comprises a controller, a clock generation circuit and a power supply circuit. The controller detects whether a condition exists to scale the voltage and frequency of the electronic device and in response, signals the clock generation circuit to perform frequency scaling on the electronic device and the power supply circuit to perform voltage scaling on the electronic device. The condition may include a situation where the temperature of the electronic device is detected to have exceeded a thermal band. The condition may also include a situation where the electronic device is detected to be idle for a selected percentage of its run time.

Apparatus and method for controlling power usage

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Mountain View, CA, United States of America

Ketan S Bhat