Samsung Electronics Co., Ltd.

Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Keshavan Varadarajan

David Conrad Tannenbaum

Veynu Narasiman

Ankur Deshwal

Soma Kohli

Ranjani Narayan

Soojung Ryu

Jeongae Park

Seokyoon Jung

Vikash Kumar

F N U Gurupad

Srinidhi Padmanabhan

Somya Singhal

Mookyoung Chung

Gautham Natanasabapathy

Parikshit Kolipaka

A method of packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique. The indication may include one or more of: an importance, a quality, a level of interest, a level of detail, or a variable-rate shading (VRS) level. The indication may be received from an application. The packing technique may include array merging. The array merging may include quad merging. The packing technique may include pixel piling. The packing technique may be a first packing technique, and the method may further include determining, based on the indication, a second packing technique for the portion of the image, and packing coverage for the portion of the image based on the second packing technique.

Methods and apparatus for pixel packing

A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.

Method for performing shader occupancy for small primitives

A method of executing an early-Z draw call in a graphics processing pipeline may include detecting a late-Z draw call in the pipeline, determining a compatibility of a depth comparison function of the early-Z draw call with a depth comparison function of the late-Z draw call, and speculatively executing a fragment of the early-Z draw call with a shader. The method may further include determining that the fragment of the early-Z draw call passes the depth comparison function of the early-Z draw call, and updating a depth buffer with a depth value for the fragment of the early-Z draw call. The method may further include determining that the fragment of the early-Z draw call provides a correct result, and forwarding the speculative shader result for the fragment to a next stage of the pipeline.

Methods and apparatus for speculative execution of fragments in a graphics pipeline

A binning subsystem of a GPU includes a storage subsystem, a shader core to output first data via a first path, a selector to receive the first data via the first path, and to receive second data from the storage subsystem via a second path. The storage subsystem includes a binner unit and a control logic unit. The control logic unit causes the selector to transfer the first data or the second data to the binner unit. The binner unit may transfer binner output data to the shader core via a third path. The binner unit may transfer the binner output data to one or more subsequent stages of a graphics pipeline via a fourth path. The binner unit may transfer the binner output data to the storage subsystem via a fifth path. The control logic unit may control the binner unit such that the binner unit can be used for general purpose computation.

Shader accessible configurable binning subsystem

A system and a method are disclosed for ray tracing in a pipeline of a graphic processing unit (GPU). It is determined whether a ray bounce of a first ray intersects a first primitive that is the closest primitive intersected by the ray bounce. The first ray is part of a first group of rays being processed by a first single-instruction-multiple-data (SIMD) process. The first ray is assigned by a sorting or binning unit to a second group of rays based on the intersection of the first primitive. The second group of rays is processed by a second SIMD process. The first ray is assigned to the second group of rays based on a material identification of the first primitive, an identification of the first primitive intersected by the ray bound of the first ray, a pixel location, and a bounce number of the ray bounce intersecting the first primitive.

Method for ray intersection sorting

A method and apparatus to construct a bounding volume hierarchy (BVH) tree includes: generating 2-dimensional (2D) tiles including primitives; converting the 2D tiles into 3-dimensional (3D) tiles; and constructing the BVH tree based on the 3D tiles.

System and method of constructing bounding volume hierarchy tree

Provide are a methods and devices for processing graphics data in a graphics processing unit (GPU). The method of processing graphics data includes receiving, at a processor, a difference of Gaussian (DOG) layer of an image, detecting, from the received DOG layer, a candidate DOG layer of the image as an intermediate layer, detecting at least one extreme point by comparing values of the candidate DOG layer with values of a previous DOG layer and a next DOG layer, and storing the at least one extreme point in a buffer.

Method and device for processing graphics data in graphics processing unit

Computing apparatus and methods are provided for performing a tile-based graphics pipeline. The graphics pipeline includes a binning pipeline configured to generate a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and a rendering pipeline configured to render an object, per tile, based on the tile list generated in the binning pipeline. Each of the binning pipeline and the rendering pipeline is configured to implement a tessellation pipeline. The graphics pipeline may be configured to operate in an efficiency mode to defer or lower tessellation by performing tessellation in one of the binning and rendering pipelines or by setting a new lower tessellation factor.

Graphic processing unit and method of performing, by graphic processing unit, tile-based graphics pipeline

Fatal errors are uncorrectable errors in hardware, which cause entire applications to be restarted and at worst can cause machine reboots. A method of recovering from a fatal error in a system having a plurality of components, in which the system includes a processor for executing a plurality of processes, comprises detecting an error in the system, determining which of the components caused the error, isolating processes affected by the error and recovering from the error. Assistance in error recovery can be provided by designing processes using check pointing, in which a back up of data pages is taken at predetermined points in a process, so that minimal loss of transactions occurs in the case of a fatal error.

Methods and apparatus for recovering from fatal errors in a system

The computer availability is predicted by determining a hazard fail rate for the computer system that is based on the hazard fail rate of the individual computer components and the computer system structure s, as well as the mean repair rate for the system. The computer hazard rates of individual computer system components are based on the error monitoring of those computer components during the computer system operation in real time.

Growing community of inventors

Bengaluru, India

Keshavan Varadarajan