International Business Machines Corporation

Applied Materials, Inc.

Olin Corporation

Cyrix Corporation

Keshav B Prasad

Madhavan Swaminathan

Eric D Perfecto

Chandrika Prasad

George E White

Gordon J Robbins

Michael F McAllister

James A McDonald

Yan Ye

Laertis Economikos

James S Papanu

Kwong Hon Wong

Thomas Anthony Wassick

Sudipta Kumar Ray

Diana Xiaobing Ma

Gerald Zheyao Yin

Mukta S Farooq

Daniel George Berger

Paul R Hoffman

Umar M Ahmad

Steve S Mak

Danny Chien Lu

Thomas Caulfield

Sean T Crowley

Susan J LaMaire

Ananda Kumar

Paul Martinez

Mark Siegel

A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Thin film wiring scheme utilizing inter-chip site surface wiring

A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Minimal capture pads applied to ceramic vias in ceramic substrates

The present invention provides an apparatus and process for plasma cleaning the interior surfaces of semiconductor processing chambers. The method is directed to the dry etching of accumulated contaminant residues attached to the inner surfaces of the plasma processing chamber and includes introducing a cleaning gas mixture of a halogen-containing gas; activating a plasma in an environment substantially free of oxygen species; contacting the contaminant residues with the activated cleaning gas to volatilize the residues; and removing the gaseous by-products from the chamber. The etchant gaseous mixture comprises an even or greater amount of at least one fluorine-containing gas and an even or lesser amount of at least one chlorine-containing gas. The instant invention enables the intermittent use of the cleaning steps in an ongoing plasma processing of semiconductor wafers without chamber downtime and significant loss of wafer production.

Method and apparatus for cleaning by-products from plasma chamber

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Method for repairing defective electrical connections on multi-layer

An electronic package with a semiconductor chip, a lead frame, a metal casing, and a redistribution interposer. The chip is mounted on the interposer and wirebonded to first ends of redistribution leads of the interposer. The redistribution leads have second ends orientated in a general flipped orientation relative to their corresponding first ends. The second ends are wirebonded to pads of the lead frame. The interposer allows smaller chips to be used in the package without changing the lead frame. The interposer also allows the chip to be flip-mounted in the package without changing the lead frame or casing, this allows redirection of the chip's thermal path.

Semiconductor package with chip redistribution interposer

A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

Thin-film wiring layout for a non-planar thin-film structure

In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

Selective plating method for forming integral via and wiring layers

Growing community of inventors

Santa Clara, CA, United States of America

Keshav B Prasad