International Business Machines Corporation

Kerstin Claudia Schelm

Silvia Melitta Mueller

Petra Leber

Cedric Lichtenau

Michael Klein

Stefan Payer

Klaus Michael Kroener

Steven R Carlough

Reid T Copeland

Juergen Haess

Michael Klaus Kroener

Christophe J Layer

Xin Guo

Nicol Hofmann

Manuela Niekisch

Eric M Schwarz

Maarten Jakob Boersma

Jochen Preiss

Razvan Peter Figuli

Timothy John Slegel

Erwin F Pfeffer

Ute Gaertner

Cédric Lichtenau

Jonathan D Bradbury

Anthony Saporito

Xiao Lin Sun

Kailash Gopalakrishnan

Gregory William Alexander

Bruce C Giamei

Frank Siegfried Lehnert

Jens Leenstra

Norbert Hagspiel

Ankur Agrawal

Andreas Wagner

Nicolas Maeding

Tobias Gemmeke

John D MacDougall

K Michael Kroener

An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and obtaining a plurality of test controls using a field of the instruction. The one or more test controls of the plurality of test controls are used to specify which digit positions of the source value are to be tested for validity and what codes are valid codes for the digit positions specified to be tested. Validity testing of at least a portion of the source value is performed based on the plurality of test controls obtained using the field of the instruction, and the performing the validity testing provides a result. The result is provided for use in further processing.

Vector test decimal instruction for validity testing

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

Rounding hexadecimal floating point numbers using binary incrementors

Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

Verifying the correctness of a leading zero counter

A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.

Repurposed hexadecimal floating point data path

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Vector convert hexadecimal floating point to scaled decimal instruction

An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.

Hexadecimal floating point multiply and add instruction

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Condition code anticipator for hexadecimal floating point

An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Decimal scale and convert and split to hexadecimal floating point instruction

An aspect includes generating a data result and a special case indicator based on an instruction and at least one input data operand. Outputting the data result to a processor core. Outputting the first condition code to the processor core prior to outputting the data result to the processor core. Generating a second condition code based on the data result and the special case indicator. Performing a check by comparing the first condition code and the second condition code and flagging an error to the processor core upon the first condition code being different from the second condition code.

Efficient checking of a condition code anticipator for a floating point processor and/or unit

A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.

Instruction scheduling during execution in a processor

A method is provided. The method is executable by a processor. The method includes receiving, by an instruction issue unit of the processor as an input, a preferred instruction variant from an instruction variant selection logic. The method includes executing, by an execution unit of the processor, the preferred instruction variant. The method includes providing, by the execution unit of the processor, quality feedback to the instruction variant selection logic and evaluating, by the instruction variant selection logic of the processor, the preferred instruction variant based on the quality feedback.

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.

Hexadecimal exponent alignment for binary floating point unit

A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y' by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y&#x2032; to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.

Floating point unit for exponential function implementation

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

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Kerstin Claudia Schelm