Intel Corporation

Kerry Vander Kamp

Anand K Enamandram

Rahul Khanna

Mahesh S Natu

Robert A Branch

Wei P Chen

Yen-Cheng Liu

Monam Agarwal

James Goffena

Jason Voelz

Wei Chen

Rita Deepak Gupta

An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

Interleaving of heterogeneous memory targets

Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Accessing a memory using index offset information

Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.

Technology to ensure sufficient memory type range registers to fully cache complex memory configurations

Techniques for using a controlling computer to control another computer with special instruction package prior to launch of the operating system in the controlled computer. For example, a method includes operating the package prior to running the OS in the controlled computer, using the package to cause the controlled computer to respond to a command from the controlling computer, using the package to generate a video frame to represent the received command and the generated response in two separate fields, and sending data for the video frame to the controlling computer. The package may be a special BIOS instruction set. The two separate fields have different coordinates and data bits representing the command are in the designated command field. In operation, the special BIOS set extracts a command from the data bits in the designated command field for execution according to the coordinates of the data bits.

Remote control of a linked computer

Redirection of accesses to non-existent memory is instead sent to a virtual buffer. The virtual buffer may be implemented in headless systems which include no video buffer. Console redirection may use the virtual buffer to display information about the headless system. Accesses to the non-existent video hardware, either directly or using the BIOS API, are redirected to the virtual buffer before being retrieved by a remote console. The headless system is cheaper and may support additional add-in cards because the system includes no video controller.

Growing community of inventors

Hillsboro, OR, United States of America

Kerry Vander Kamp