International Business Machines Corporation

Globalfoundries Inc.

Kerry Christopher Imming

John David Irish

Tolga Ozguner

Joseph Franklin Logan

Paul Allen Ganfield

Kent Harold Haselhorst

Jean Louis Calvignac

Michael Steven Siegel

Marco C Heddes

Andrew Henry Wottreng

Ryan Abel Heckendorf

Christopher Jon Johnson

Anthony Gus Aipperspach

James Francis Mikos

Matthew Roger Ellavsky

Morgan D Davis

Ibrahim Abdel-Rahman Ouda

Gerald G Fagerness

Brian M McKevett

Mark G Veldhuizen

Emmanuel Sacristan

Resham Rajendra Kulkarni

To Dieu Liang

Sarah Sabra Pettengill

The present disclosure includes mapping redundant addresses in a multi-node system by receiving a first address and a first node ID, determining a first address type representing an address redundancy level for the first address, determining a first node ID type representing a node ID redundancy level for the first node ID, and determining a second address and a second node ID based on the first address type and the first node ID type.

Redundant location address mapper

A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.

Implementing lane shuffle for fault-tolerant communication links

A method and elastic buffer circuit are provided for implementing low power, single master-slave elastic buffers in a network chip design to provide a continuous stream of data to multiple sinks from multiple sources, and a design structure on which the subject circuit resides. An elastic buffer only uses a single master-slave register. The circuit includes a finite state machine, and a latch control block (LCB) to implement the single master-slave elastic buffer removing all &#xbd; cycle paths between buffer locations enabling usage of the single master-slave register.

Implementing low power, single master-slave elastic buffer

A method and circuit for implementing exchange of failing lane information for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. An ordered set for lane and link training includes a novel lane mask field for lane and link training. Ordered sets are exchanged during lane and link training for a fault-tolerant communication link to establish synchronization between a transmitter and a receiver. In a link training step, the bus link layer exchanges an ordered set with a plurality of bits of lane mask information included in predefined bytes, such as bytesandof the lane mask field. Upon receiving the ordered set with the plurality of bits of lane mask information, the transmitter lanes are reconfigured to align with the received mask information.

Implementing exchange of failing lane information for fault-tolerant communication links

A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.

Methods and apparatus for indexing memory of a network processor

A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

Implementing pointer and stake model for frame alteration code in a network processor

A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.

Implementing conditional packet alterations based on transmit port

A method, apparatus and computer program product are provided for implementing virtual packet storage via packet work area (PWA) in a network processor system. A mapping area including a packet work area and a corresponding set of packet segment registers (PSRs) are provided. A PSR is loaded with a Packet ID (PID) and a packet translation unit maps the packet data into the corresponding PWA. The PWA address defining an offset into the packet is translated into a physical address. The packet translation unit redirects loads and stores of the PWA into the correct data buffer or buffers in system memory. Packets include one or more data buffers that are chained together, using a buffer descriptor providing the packet physical address. The buffer descriptor points to a data buffer for the packet and to a next buffer descriptor.

Implementing virtual packet storage via packet work area

A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result. Otherwise, the master tester generates a fail result. In one embodiment, the DUT includes multiple receivers and the system determines a pass/fail rating on a per receiver basis.

Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer

A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.

Method and apparatus for implementing packet command instructions for network processing

Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor

A method, apparatus, and computer program product are provided for implementing packet ordering in a network processor. Packets are received and placed on a receive queue and a queue entry is provided for each received packet. The queue entry includes for each autoroute packet, an autoroute indication and a selected transmit queue. An associated ordering queue is provided with the receive queue. A software-handled packet is dequeued from the receive queue and the dequeued software-handled packet is placed on the ordering queue. Each autoroute packet reaching a head of the receive queue is automatically moved to the selected ordering queue.

Method, apparatus, and computer program product for implementing packet ordering

In a first aspect, a method for maintaining control structure coherency is provided. The method includes the steps of (1) writing a pointer to a control structure in a hardware update list while one or more portions of the control structure are accessed by hardware during a hardware update operation; and (2) delaying a software access to one or more portions of the control structure during a software update operation while the pointer to the control structure is on the hardware update list. Numerous other aspects are provided.

Methods and apparatus for maintaining coherency in a multi-processor system

In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter in main memory is updated using the cache memory counter value. This arrangement economizes on the use of main memory access bandwidth.

Growing community of inventors

Rochester, MN, United States of America

Kerry Christopher Imming