Texas Instruments Corporation

Kerry C Glover

Krishnasawamy Nagaraj

Davy H Choi

Sami Kiriaki

Mark A Wolfe

Glenn C Mayfield

Benjamin Joseph Sheahan

Jefferson W Gamble

A method for acquiring a signal in a read channel ( ), the read channel ( ) having an equalizer ( ), includes performing an automatic gain control sequence; performing a phase locked loop sequence that includes performing a fast phase locked loop step, the fast phase locked loop step including bypassing the equalizer; and performing a synchronization search sequence.

Method and circuitry for acquiring a signal in a read channel

A server hard disk drive integrated circuit (,) is provided for controlling the operation of a server hard disk drive (,) and for processing digital data exchanged between a client (,) and a storage media. The storage media includes a spindle motor for rotating a magnetic disk and a head actuator for positioning a read/write head. The server hard disk drive integrated circuit (,) includes a RAM (,), a disk control circuitry (,), write channel (,), a read channel (,), a servo circuit (,), a motor control circuit (,), and a DSP (,). The disk control circuitry (,) receives and stores requests provided from the client (,) and exchanges digital data with the client (,) and stores the digital data in RAM (,). The write channel (,) generates a write signal during a write operation, and the read channel (,) generates a read signal and an intermediate read signal during a read operation. The servo circuit (,) generates a servo signal during a servo operation, and the motor control circuit (,) receives a motor control input signal and generates a motor control output signal to control the spindle motor and the head actuator. Finally, the digital signal processor (,) initiates the read and write operations as needed to perform the requests of the client. The digital signal processor (,) also performs file management, generates the motor control input signal, and processes the intermediate read signal to generate a read channel parameter.

Server hard disk drive integrated circuit and method of operation

A metric circuit (,) and method for use in a viterbi detector (,) are provided. The metric circuit (,) provides a transition signal (,) to a trellis block (,) during a first period and a second period. The transition signal (,) includes a negative transition signal and a positive transition signal. The metric circuit (,) includes a first adder circuit (,), a second adder circuit (,), a first comparator (,), a second comparator (,), an odd sample/hold circuit (,), and an even sample/hold circuit (,). The metric circuit (,) receives a discrete signal and a threshold value at the first adder circuit (,) and the second adder circuit (,). The first is adder circuit (,) generates a first sum and the second adder circuit (,) generates a second sum. The first comparator (,) compares the first sum to an odd metric value, stored in the odd sample/hold circuit (,), during the first period, and compares the first sum to an even metric value, stored in the even sample/hold circuit (,), during the second period. The second comparator (,) compares the second sum to the odd metric value during the first period, and compares the second sum to the even metric value during the second period. The value of the odd metric value and the even metric value are replaced with either the first sum or the second sum only when specified conditions are met.

Metric circuit and method for use in a viterbi detector

A read channel (18) is provided for use in a mass storage system. The read channel (18) includes a plurality of circuit modules and an error estimation circuit (50). The plurality of circuit modules receive an analog data signal from a disk/head assembly (12) and condition the signal to provide a digital data signal. The error estimation circuit (50) receives an analog signal from one of the plurality of circuit modules and analyzes the analog signal. The error estimation circuit (50) provides digital error signal (94) and digital level estimation signal (96) as a result.

Error estimation circuit and method using an analog-to-digital converter

A servo demodulator (20) is provided for generating a track identification signal (148) and a position error signal (150) from a servo wedge signal, such as a filtered servo wedge signal (112), in response to the processing of the servo wedge signal by a read channel (18). The servo demodulator (20) includes a servo clock generation circuit (90), a position error signal circuit (92), and a track identification circuit (76). The servo clock generation circuit (90) generates a synchronous servo clock signal (102) in response to receiving a servo reference clock signal (110) and the filtered servo wedge signal (112). The synchronous servo clock signal (102) is provided to the read channel (18) for use in processing the servo wedge signal. The position error signal circuit (92) generates the position error signal (150) in response to receiving the synchronous servo clock signal (102) from the servo clock generation circuit (90) and a synchronously sampled servo wedge signal (114) from the read channel (18). The read channel (18) generates the synchronously sampled servo wedge signal (114) by using the synchronous servo clock signal (102) to synchronously sample the servo wedge signal. The track identification circuit (76) generates the track identification signal (148) in response to receiving a digital servo wedge signal (116) from the read channel (18).

Servo demodulator and method for synchronous servo demodulation

A data synchronization method and circuit are provided. A data synchronization circuit (28) includes a header timer (40), a timeout counter (44), a compare circuit (46), and a synchronization field register (48) for use in a read channel (10). During a read operation in the read channel (10), the data synchronization circuit (28) searches for the presence of a synchronization field in a read signal indicating that user data will be provided next. The search occurs over a predefined period of time. The header timer (40) enables a header timer signal for a first predefined period of time. The timeout counter (44) receives the header timer signal and enables a timeout counter signal for a second predefined period of time after the first predefined period of time expires. The compare circuit (46) compares the read signal to the known value or synchronization field stored in the synchronization field register (48). This comparison occurs during the second predefined period of time, the time in which the timeout counter signal is enabled to determine if a synchronization field is present in the read signal. Finally, the compare circuit (46) provides a synchronization detect signal that indicates whether a synchronization field was found during the second period of time.

Data synchronization method and circuit using a timeout counter

A detector and method for detecting defects in the magnetic media of a disk drive mass storage system (30) are provided. The detector may include a viterbi detector (54), having a metric circuit (53) and a trellis circuit (55), for use in a read channel (18) during read operations. Known data is originally written to a sector of the magnetic media of a disk/head assembly (12). The known data includes all binary 'ones.' The sector of known data is later read during a read operation. During this read operation, the read channel (18) receives an analog signal corresponding to the sector of known data. The metric circuit (53) receives a discrete, equalized signal from a finite impulse response filter (48) and provides a transition signal (56). The transition signal (56) is provided to a control circuitry (11) through a data/parameter path (13) after being placed in parallel format by a deserializer (60). A microprocessor (28) of the control circuitry (11) may process the transition signal (56) and determine which of the bits of the transition signal (56) are different from the original known data. Discrepancies indicate the existence and location of a defect in the magnetic media.

Detector and method for detecting defects in the magnetic media of a

A novel Finite Impulse Response ('FIR') filter (10)' is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

Fir filter architecture with precise timing acquisition

A read channel (18) for use in a mass storage system is provided. The read channel (18) includes a plurality of circuit modules circuit and an error estimation circuit (50). The plurality of circuit modules may include circuitry such as a VGA (40), an LPF (42), and an equalizer (48), for conditioning an analog data signal. The plurality of circuit modules receive the analog data signal from a disk/head assembly (12) and condition the signal to generate a digital data signal. The error estimation circuit (50) receives an analog signal from one of the plurality of circuit modules, such as the equalizer (48), and analyzes the analog signal to generate an analog error output signal (94) that is used in the read channel (18) and provided to external circuitry.

Error estimation circuit and method for providing a read channel error

An automatic gain control circuit (44) is provided for generating an output gain signal (64) in a control loop. The control loop may a continuous-time control loop or a sampled-time control loop. The automatic gain control circuit (144) includes a gain control circuit (100), an amplifier circuit such as a first amplifier (120) or a second amplifier (122), a control circuit (126), and a low pass filter (84). The gain control circuit (144) receives a read signal and generates an error signal in response. The first amplifier (120) receives the error signal and generates an amplified error signal. The control circuit (126) controls various switches, such as a first switch (100) and a second switch (102), so that the amplified error signal and the error signal may be provided to the low pass filter (84) during different periods. The amplified error signal is provided during a first period that is shorter than the response time of the control loop. The error signal is provided next after the first period and after a second period that is longer than the response time of the control loop. The low pass filter (84) filters these signals and generates the output gain signal (64).

Automatic gain control circuit and method for full gain restart

A read channel (18) having a waveform sampler (58) is provided for use in a disk drive mass storage system (30). The disk drive mass storage system (30) includes a disk/head assembly (12), a preamplifier (14), and a control circuitry (11). The read channel (18) is coupled to the control circuitry (11) through a data/parameter path (13). The read channel (18) includes a plurality of circuit modules for processing a waveform data signal received from the preamplifier (14) and to generate a digital data signal in response. The read channel provides the digital data signal to the control circuitry (11) through the data/parameter path (13). The read channel (18) also includes the waveform sampler (58) for receiving and sampling a processed waveform signal from one of the plurality of circuit modules and for generating a digital waveform sampler signal in response. The read channel can provide either the digital data signal or the digital waveform sampling signal as an output onto the data/parameter path (13).

Waveform sampler and method for sampling a signal from a read channel

A phase locked loop system (52) and method is used in a synchronously sampled data channel (10) of a disk drive mass storage system (30).

Phase locked loop system and method for use in a data channel

An automatic gain control circuit (44) is provided for generating an output gain signal. The automatic gain control circuit (44) includes a full-wave rectifier (70), an adder circuit (74), a multiplier circuit (82), and a low pass filter (86). The full-wave rectifier (70) receives a continuous-time read signal and generates a rectified read signal that is provided to the adder circuit (74). The adder circuit (74) generates an offset signal by taking the difference between the rectified read signal and a threshold signal. The offset signal is provided to the multiplier circuit (82) which multiplies the offset signal by a gain signal, such as a first gain signal or a second gain signal, to generate an error signal. A selection circuit, such as a multiplexer (76), may be provided to determine whether to provide the first gain signal or the second gain signal to the multiplier circuit (82). The multiplexer (76) may be controlled by a comparator (72) that generates a signal indicating whether the rectified read signal is above or below a threshold signal or value. The low pass filter (86) receives the error signal and generates the output gain signal of the automatic gain control circuit (44).

Automatic gain control circuit and method

An electronic circuit used in the control and operation of a mass storage system (30) is provided that includes an SSD channel (10), and a control circuitry (11) having a microprocessor (28) and a read only memory (ROM) (29). During an initialization routine, microprocessor (28) and the ROM (29) of the control circuitry (11) provide operational parameters to the SSD channel (10) through a data/parameter path (13). The SSD channel (10) receives these operational parameters and stores them in a parameter memory (22) so that a read channel (18) may access the operational parameters during read operations. During read operations, the read channel (18) receives a stored data signal from a disk/head assembly (12) and a preamplifier (14). The read channel (18) processes the stored data signal and provides an output digital data signal. The digital data signal is provided to the control circuitry (11) through the data/parameter path (13). Thus, at different times, the operational parameters and the digital data signal are both exchanged through the data/parameter path (13).

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Wylie, TX, United States of America

Kerry C Glover