International Business Machines Corporation

Globalfoundries Inc.

Kerry Bernstein

Anthony K Stamper

Norman Jay Rohrer

Paul David Kartschoke

Timothy Joseph Dalton

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Edward J Nowak

Philip George Emma

Clarence Rosser Ogilvie

Jeffrey P Gambino

Mark David Jaffe

Wilbur David Pricer

Bruno Michel

Thomas J Brunschwiler

Keith Robert Williams

John Edward Barth, Jr

William A Klaasen

Paul William Coteus

Stephen Ellinwood Luce

Andres Bryant

John Atkinson Fifield

Stephen Victor Kosonocky

Francis Roger White

Tak H Ning

John J Ellis-Monaghan

Steven H Voldman

Ruchir Puri

William J Cote

Mark B Ritter

John Anthony Bracchitta

BethAnn Rainey

Charles S Woodruff

Edmund Juris Sprogis

Wilfried Haensch

Robert L Wisnieff

Nazmul Habib

Peter Anthony Sandon

Robert Michael Geffken

Ethan Harrison Cannon

Stephen Arthur St Onge

Peter Edwin Cottrell

Stephen W Bedell

Daniel C Edelstein

Terence B Hook

Timothy Harrison Daubenspeck

Wolfgang Sauter

Katherine Lynn Saenger

Christopher David Muzzy

Jack Oon Chu

Daniel Joseph Friedman

Sri Muthuthamby Sri-Jayantha

Igor Arsovski

Peter Juergen Klim

Min Yang

Richard Quimby Williams

Wayne John Howell

Harold John Hovel

Christopher McCall Durham

James A Culp

Douglas Willard Stout

Eric Francis Robinson

David S Wolpert

Albert M Young

Allan Mark Hartstein

Alvin Wayne Strong

Donald Lawrence Wheater

Jeannine Madelyn Trewhella

Christy Sensenich Tyberg

Ibrahim M Elfadel

Ernest Y Wu

Marc Raymond Faucher

Ronald Jay Bolam

Michael Ignatowski

Brent A Anderson

Rajiv V Joshi

Jeffrey W Sleight

Robert J Gauthier, Jr

Kirk David Peterson

Dirk Pfeiffer

Peilin Song

Kevin John Nowka

John Maxwell Cohn

Anthony Richard Bonaccio

Randy William Mann

Anthony Correale, Jr

Franco Stellari

Michael John Hargrove

Minh H Tong

Fariborz Assaderaghi

David Meltzer

Josef S Watts

Stephen Dale Wyatt

Anthony D Polson

Leendert M Huisman

Jason Alan Cox

Moinuddin K Qureshi

Eric Adler

Leah M P Pastel

Richard Andre Wachnik

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, a system board configured to be electrically connected to the casing, and upper and lower cards connected to the casing for electrically connecting the casing to the system board.

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. Opposing edges of the upper card are located between vertical planes defined by the outer sidewalls of the upper portion of the casing.

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The outer sidewalls of the upper portion of the casing are located between vertical planes defined by opposing outer sidewalls of the lower portion of the casing.

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing.

A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.

System and method of masking electromagnetic interference (EMI) emissions of a circuit

A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit

A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror.

Reactive metal optical security device and methods of fabrication and use

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output.

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Methods for normalizing strain in semicondcutor devices and strain normalized semiconductor devices

An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

Detecting chip alterations with light emission

An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.

Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof

A method of dissipating heat from a heat source includes providing a plurality of heat flux paths in a plane of the heat source to remove heat from the heat source.

In-plane silicon heat spreader and method therefor

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Underhill, VT, United States of America

Kerry Bernstein