Ceridian Corporation

Kermit E Frye

James A Dahlberg

David G Fangmeier

Larry M Werlinger

A direct memory access (DMA) controller having a first mode and a second mode controls communication between a module bus, communicating with a processor and a memory, and an input/output (I/O) bus communicating with an external device. A data controller subsystem stores I/O bus input data to provide module bus output data, and stores module bus input data to provide I/O bus output data. A device address controller subsystem stores a device address from the module bus to provide an I/O device output address to the I/O bus for addressing the external device. A memory addressing subsystem receives module bus input data to form an initial memory address provided to the module bus representing a storage location in the memory. An incrementer increments the initial memory address. In the second mode, the incrementer restarts the memory address at the initial memory address after incrementing the memory address a selected number of addresses above the initial memory address to form a wrap-around buffer in the memory. A transfer counter calculates a transfer count representing the number of selected data groupings of the I/O bus output data written into the memory. A detector detects when the transfer count reaches a selected value indicating that a normal DMA operation is complete in the first mode and detects when the wrap-around buffer in the memory is full based on the transfer count in the second mode.

DNA controller with wrap-around buffer mode

A priority selector prioritizes interrupts associated with each ASIC of a plural ASIC system in accordance with a programmed sequence. A table in each ASIC contains a programmable offset table and a programmable priority code table. The table selects an offset value and a priority code associated with the highest priority interrupt for the ASIC. An interrupt collector includes a priority compare to identify the priority code of the highest-priority interrupt of all of the ASICs. A multiplexer selects the offset value associated with it. The offset value forms a jump or offset address to the interrupt for the CPU. The priority sequencing, offset tables, priority code tables and priority compare values are programmable, so the prioritizing is adjustable. Each priority selector generates an interrupt active signal for the CPU. A mask disables interrupts until serviced by the CPU so that any interrupt active signal resulting from a disabled interrupt is terminated.

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Bloomington, MN, United States of America

Kermit E Frye