Cavium, Inc.

Marvell Asia Pte., Ltd.

Keqin Han

Saurin Patel

Nimalan Siva

Vamsi Panchagnula

Tsahi Daniel

Mohan Balan

Polasanapalli Sri Devi

Sri Devi Polasanapalli

An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.

Method and apparatus for using multiple linked memory lists

An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams. A processor coupled to the ingress port, to identify source data of the multicast data packets of the data streams to match the multicast data packets with available egress ports. The processor to determine, using the identified source and status data which of the multicast data packets matches the available egress ports. The processor to select a first data path coupled to the egress port to transmit the matched multicast data packets to available egress ports where the selected first data path is configured to enable the direct transmission of the matched multicast data packets to available egress ports.

Method and apparatus for bypass routing of multicast data packets and avoiding replication to reduce overall switch latency

A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Testbench builder, system, device and method

Testbench builder, system, device and method including latency detection

Testbench builder, system, device and method having agent loopback functionality

Testbench builder, system, device and method with phase synchronization

Testbench builder, system, device and method including a generic monitor and transporter

Testbench builder, system, device and method including a dispatcher

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Fremont, CA, United States of America

Keqin Han