Altera Corporation

Intel Corporation

Keong Hong Oh

Chooi Pei Lim

Yee Liang Tan

Siang Poh Loh

Teik Wah Lim

Boon Haw Ooi

Siang Poh Lob

The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.

Clock synchronization in multi-die field programmable gate array devices

Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Multi-layer distributed network

Growing community of inventors

Bayan Lepas, Malaysia

Keong Hong Oh