Samsung Electronics Co., Ltd.

Keon-Han Sohn

Sang-Bum Kim

Sang-Wook Kang

Chang-il Son

Si-Yung Park

Yong-Ji Kim

Soong-Sung Kwon

A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a non-volatile memory interface circuit for transferring/receiving a signal to/from the internal circuit in synchronization with the first clock and transferring/receiving the signal to/from an external device in synchronization with a second clock that is asynchronous relative to the first clock.

Smart cards including separate clocks for key processing and non-volatile memory interface communications and methods of operating the same

Provided are a semiconductor device and a data transmitting method thereof. The method includes transmitting data into a memory through at least one data line, scrambling the data corresponding to at least one mask data, and determining, using the at least one mask data, data integrity of the data transmitted through the at least one data line. The method may also include storing the data transmitted through the at least one data line in the memory according to a data integrity determination result.

Semiconductor devices and scrambled data transmission methods thereof

An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal, a second buffer for receiving data from the flash memory device in synchronization with the clock enable signal, a third buffer for receiving and outputting an output of the first buffer, and a latch circuit for latching an output of the second buffer in synchronization with output of the third buffer.

Flash memory controller

A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.

Growing community of inventors

Yongin-si, South Korea

Keon-Han Sohn