Intel Corporation

Kenzo Van Craeynest

Aamer Jaleel

Paolo L Narvaez

Efraim Rotem

Eliezer Weissmann

Alon Naveh

Ronny Ronen

Boris Ginzburg

Dheeraj R Subbareddy

Eugene Gorbatov

Joel S Emer

David A Koufaty

Michael Mishaeli

Anil Aggarwal

Scott D Hahn

Yuval Yosef

Tong Li

Hisham Abu-Salah

Ilya Osadchiy

Avi Mendleson

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

A processor is described having an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread. The processor also includes statistics collection circuitry to support calculation of the following: the first thread's performance on the out-of-order core; an estimate of the first thread's performance on the non-out-of-order core; the second thread's performance on the non-out-of-order core; an estimate of the second thread's performance on the out-of-order core.

Processor scheduling with thread performance estimation on cores of different types

Growing community of inventors

Waregem, Belgium

Kenzo Van Craeynest