Renesas Electronics Corporation

Nec Corporation

Kenzo Tan

Masahiro Takeuchi

Kazuhisa Sunaga

A semiconductor device including a detector to compare an amplitude of an applicable signal with a specified threshold amplitude, and to output a detector output indicating whether or not the amplitude of the applicable signal is above a specified threshold amplitude, and an intermittent operation control circuit that receives the detector output, and also receives a first signal showing which mode among the multiple modes the standby mode state is in, and sets the detector to the on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector according to characteristics of the input signal in the mode shown by the applicable first signal.

Setting the detector to the continuously on mode or intermittently operating based on the amplitude of an input signal

An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit time, a first delay circuit to delay an output signal of the first discrimination circuit and that includes N-number (N&#x3e;=2) of stages of unit delay circuits connected in cascade and operating in unit time, a second delay circuit to receives an output signal of the second discrimination circuit and that includes not less than an (N+1)-number of stages of unit delay circuits connected in cascade and operating in unit time, and a control unit that receives an output of the first delay circuit, and a second output signal output from the second delay circuit.

Equalizer and semiconductor device

A semiconductor device includes a detector that receives an input signal whose characteristics fluctuate depend on the standby mode state, compares the input signal amplitude with a specific threshold amplitude, and outputs a detector output signal that shows whether or not the amplitude of the applicable input signal is above the specified threshold amplitude; and an intermittent operation control circuit that along with receiving the detector output, also receives a first signal showing which mode among the multiple standby mode states is in, and sets the detector to the continuously on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector depend on the characteristics of the input signal in the mode shown by the first signal.

Method for power saving during standby mode in the physical layer block for the serial data communication interface

Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data. The pattern filter selects one of the edge decision data sampled at the odd edge timing and at the even edge timing in response to the value of a data pattern of three consecutive bits obtained from the data decision data sampled at the odd and even data timings.

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Kawasaki, Japan

Kenzo Tan