Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Kenzo Kurotsuchi

Norikatsu Takaura

Motoyasu Terao

Riichiro Takemura

Hideyuki Matsuoka

Nozomu Matsuzaki

Yoshitaka Sasago

Takahiro Morikawa

Takayuki Kawahara

Satoru Hanzawa

Seiji Miura

Masaharu Kinoshita

Yoshihisa Fujisaki

Akio Shima

Tsuyoshi Yamauchi

Yuichi Matsui

Mitsuharu Tai

Hiroshi Uchigaito

Osamu Tonomura

Takashi Kobayashi

Toshiyuki Mine

Hiromasa Takahashi

Shirun Ho

Sanato Nagata

Hiroyuki Minemura

Kiyoo Itoh

Kenichi Osada

Masanao Yamaoka

Naoki Yamamoto

Masahiko Ando

Tatsuya Tomaru

Seiichi Suzuki

Junichi Miyakoshi

Yuji Suwa

Norifumi Kameshiro

A computing apparatus that does not need quantum coherence or a cryogenic cooling apparatus is provided for assignments that need an exhaustive search. A system is led to the ground state of the system where a problem is set, wherein spin sthat is a variable follows a local effective magnetic field B. The spin state at t=0 is initialized with a transverse field (in the x-direction). This corresponds to s=0. With time t, the magnetic field in the z-axis direction and the inter-spin interactions are gradually added, and finally the spin is directed to the +z- or &#x2212;z-direction. The z component of the spin sis s=+1 or &#x2212;1. Here, in the process where the orientation of the spin sfollows that of the effective magnetic field B, correction parameters originating in quantum-mechanical effects are introduced and ground-state-maintaining performance is improved.

Computing apparatus incorporating quantum effects that performs high-speed computation on inverse problems or computational optimization problems requiring exhaustive search

A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

Data generation method and computer system

An object of the present invention is to provide an artificial olfactory sensing system capable of sniffing out various odors highly sensitively. The artificial olfactory sensing system includes: plural sensor cells on a lipid membrane of each of which olfactory receptors have developed; and plural ion-sensitive field-effect transistors (ISFETs) that correspondingly exist to the sensor cells on a one-on-one basis. A response signal showing that each of the olfactory receptors of each of the sensor cells has recognized an odor molecule is converted into an electric signal by an ISFET corresponding to each of the sensor cells.

Artificial olfactory sensing system

In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors. By using the semiconductor storage device, a connection pattern of a feeding electrode for the memory cells can be configured according to the magnitude of a consumption current, power consumption by a voltage drop by a parasitic resistance of the feeding electrode and power consumption by charge/discharge of a parasitic capacitance around the feeding electrode can be suppressed, and performance per consumption power in read/set/reset operations can be improved.

Semiconductor storage device

When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Nonvolatile memory device and method for manufacturing same

An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG.).

The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.

Non-volatile storage addressing using multiple tables

A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL) that is another part thereof according to a second write command with respect to the physical address.

Semiconductor device

An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Information processor

On an insulating film () in which a plug () as a lower electrode is embedded, a laminated layer pattern of an insulating film () made of tantalum oxide, a recording layer () made of Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced and an upper electrode film () made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film () between the recording layer () and the plug (), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer () can be achieved. Further, by using the Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced as the recording layer (), the difference in work function between the insulating film () and the recording layer () is increased, and the programming voltage of the phase change memory can be reduced.

For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

On the same semiconductor substrate, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layerstoring a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layeris made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Growing community of inventors

Kodaira, Japan

Kenzo Kurotsuchi