Intel Corporation

Jds Uniphase Corporation

Kenzo Ishida

Suresh Ramalingam

Douglas E Crafts

Kinya Ichikawa

James F Farrell

Shuji Inoue

Steven M Swain

David J Chapman

Mark Brian Farrelly

Yohko Mashimoto

Kenji Takahashi

Venkatesan Murali

Jyoti Kiron Bhardwaj

Daryl James Nelson

Robert Brainard

David J Dougherty

Sanjay M Thekdi

Zi-Wen Dong

Hiroaki Yamada

Anantharaman Vaidyanathan

Duane Cook

Brian A Kaiser

Thomas Nguyen

David K Nakamoto

Erik W Egan

Niranjan Gopinathan

Yingchao Yan

Shinya Endo

Anant Vaidyanathan

An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.

Apparatus and method for warpage compensation of a display panel substrate assembly

A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.

Easy mount socket

A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Compact, low insertion loss, high yield arrayed waveguide grating

A package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package, which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar light-wave circuit (PLC), e.g. an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.

Package for optical components

A groove assembly for holding at least one fiber optic. The assembly includes a base, a cover and a small carrier disposed between the base and the cover. The carrier has at least one groove. At least one fiber optic is disposed in this groove and terminates at an edge surface of the carrier. The base and cover have respective edge surfaces serving as attachment surfaces for attachment of the assembly to a planar lightwave circuit (PLC). The PLC has at least one waveguide terminating at an edge, to which the fiber requires alignment. The base and/or cover are preferably formed from a material enabling attachment to the PLC, e.g., transparent to energy used for curing an adhesive. The carrier is formed from material enabling a substantially more precise formation of the grooves, e.g., silicon.

Precision fiber optic alignment and attachment apparatus

An optical component package, in which a transfer molded layer of material (e.g., syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.

Transfer molded packages with embedded thermal insulation

A heat dissipation device comprising a thermally conductive, hollow housing having a fan and an active anti-noise module disposed within the hollow housing. The hollow housing may include a plurality of fins disposed therein to increase the surface area for convective heat transfer. The heat dissipation device further may further include heat pipes for the transportation and dispersion of heat to and about an external surface of the hollow housing.

Silent heat exchanger and fan assembly

A substrate which has a first conductive layer that is attached to a first dielectric layer. A second conductive layer is attached to the first dielectric layer. The second conductive layer may be a plated copper material that extends through a via opening of the dielectric and is attached to the first conductive layer. A third conductive layer is attached to the second conductive layer, including a sidewall of the third layer. A second dielectric can be attached to the third conductive layer. The third conductive layer may be a plated nickel-copper composition which improves the adhesion to subsequent layers in the substrate, particularly between the second dielectric and the sidewall of the second conductive layer.

Semi-additive process (SAP) architecture for organic leadless grid array packages

A cooling unit for an integrated circuit. The cooling unit may include a peltier device that may be coupled to the integrated circuit and a plurality of fins that are thermally coupled to the peltier device. The fins may be separated by at least one channel. The cooling unit may include a fan that generates a flow of fluid through the channel.

Cooling unit for an integrated circuit package

A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

Printed circuit substrate with solder formed on pad-on-via and

An method for depositing solder onto the pad-on and pad-off via contacts of a substrate is disclosed. In one embodiment the present invention includes positioning a mask having a first opening of a first diameter and a second opening of a second diameter over a substrate having both pad-on and pad-off via contacts. The substrate is positioned over the substrate such that the first opening is positioned over the pad-on via contact and the second opening is positioned over the pad-off via contact. Solder of a first volume and solder of a second volume are deposited onto the pad-on and pad-off via contacts, respectively, by forcing a solder paste through the mask openings. In this manner, solder bumps having a uniform height and volume above the pad-on via contact plane is established after reflowing the deposited solder.

Growing community of inventors

San Jose, CA, United States of America

Kenzo Ishida